var_regs.h

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#ifndef CYGONCE_HAL_VAR_REGS_H
#define CYGONCE_HAL_VAR_REGS_H

//==========================================================================
//
//      var_regs.h
//
//      PowerPC 40x variant CPU definitions
//
//==========================================================================
//####ECOSGPLCOPYRIGHTBEGIN####
// -------------------------------------------
// This file is part of eCos, the Embedded Configurable Operating System.
// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
// Copyright (C) 2002, 2003 Gary Thomas
//
// eCos is free software; you can redistribute it and/or modify it under
// the terms of the GNU General Public License as published by the Free
// Software Foundation; either version 2 or (at your option) any later version.
//
// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or
// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
// for more details.
//
// You should have received a copy of the GNU General Public License along
// with eCos; if not, write to the Free Software Foundation, Inc.,
// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
//
// As a special exception, if other files instantiate templates or use macros
// or inline functions from this file, or you compile this file and link it
// with other works to produce a work based on this file, this file does not
// by itself cause the resulting work to be covered by the GNU General Public
// License. However the source code for this file must still be made available
// in accordance with section (3) of the GNU General Public License.
//
// This exception does not invalidate any other reasons why a work based on
// this file might be covered by the GNU General Public License.
//
// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
// at http://sources.redhat.com/ecos/ecos-license/
// -------------------------------------------
//####ECOSGPLCOPYRIGHTEND####
//==========================================================================
//#####DESCRIPTIONBEGIN####
//
// Author(s):    jskov
// Contributors: jskov,gthomas
// Date:         2000-08-27
// Purpose:      Provide PPC40x register definitions
// Description:  Provide PPC40x register definitions
//               The short definitions (sans CYGARC_REG_) are exported only
//               if CYGARC_HAL_COMMON_EXPORT_CPU_MACROS is defined.
// Usage:        Included via the architecture register header:
//               #include <cyg/hal/ppc_regs.h>
//               ...
//              
//
//####DESCRIPTIONEND####
//
//==========================================================================

#include <cyg/hal/plf_regs.h>

//--------------------------------------------------------------------------
// Hardware control (usage depends on chip model)
#define CYGARC_REG_HID0   1008

#ifdef CYGARC_HAL_COMMON_EXPORT_CPU_MACROS
#define HID0       CYGARC_REG_HID0
#endif // ifdef CYGARC_HAL_COMMON_EXPORT_CPU_MACROS

//--------------------------------------------------------------------------
// MMU control.
#ifdef CYGARC_HAL_COMMON_EXPORT_CPU_MACROS

#define SPR_ESR         980            // Exception syndrome
#define SPR_EVPR        982            // Exception vector prefix
#define SPR_PID         945            // Process ID
#define SPR_CCR0        0x3B3          // Core configuration register

#define M_EPN_EPNMASK  0xfffff000      // effective page no mask
#define M_EPN_EV       0x00000040      // entry valid
#define M_EPN_SIZE(n)  (n<<7)          // entry size (0=1K, 1=4K, ... 7=16M)

#define M_RPN_RPNMASK  0xfffff000      // real page no mask
#define M_RPN_EX       0x00000200      // execute enable
#define M_RPN_WR       0x00000100      // write enable
#define M_RPN_W        0x00000008      // write-through (when cache enabled)
#define M_RPN_I        0x00000004      // cache inhibited
#define M_RPN_M        0x00000002      // memory coherent (not implemented)
#define M_RPN_G        0x00000001      // guarded

#define CYGARC_TLBWE(_id_, _hi_, _lo_) \
        asm volatile ("tlbwe %1,%0,0; tlbwe %2,%0,1" :: "r"(_id_), "r"(_hi_), "r"(_lo_));

#define CYGARC_TLBRE(_id_, _hi_, _lo_) \
        asm volatile ("tlbre %0,%2,0; tlbre %1,%2,1" : "=r"(_hi_), "=r"(_lo_) : "r"(_id_));

#endif // ifdef CYGARC_HAL_COMMON_EXPORT_CPU_MACROS

//--------------------------------------------------------------------------
// Device control register access macros.
#define CYGARC_MTDCR(_dcr_, _v_) \
    asm volatile ("mtdcr %0, %1;" :: "I" (_dcr_), "r" (_v_));
#define CYGARC_MFDCR(_dcr_, _v_) \
    asm volatile ("mfdcr %0, %1;" : "=r" (_v_) : "I" (_dcr_));

#ifdef CYGARC_HAL_COMMON_EXPORT_CPU_MACROS

// Interrupt control (device) registers
#if defined(CYGHWR_HAL_POWERPC_PPC4XX_403)
#define DCR_EXIER  66
#define DCR_EXISR  64
#define DCR_IOCR   160
#endif

#if defined(CYGHWR_HAL_POWERPC_PPC4XX_405) || defined(CYGHWR_HAL_POWERPC_PPC4XX_405GP)
// Interrupt controller
#define DCR_UIC0_SR   0xC0  // Status register
#define DCR_UIC0_ER   0xC2  // Enable register
#define DCR_UIC0_CR   0xC3  // Critical [or not]
#define DCR_UIC0_PR   0xC4  // Polarity (high/low)
#define DCR_UIC0_TR   0xC5  // Trigger (level/edge)
#define DCR_UIC0_MSR  0xC6  // Masked status
#define DCR_UIC0_VR   0xC7  // Vector
#define DCR_UIC0_VCR  0xC8  // Vector configuration

// PPC 405GP control registers (in DCR space)
#define DCR_SDRAM0_CFGADDR   0x10
#define DCR_SDRAM0_CFGDATA   0x11
#define DCR_EBC0_CFGADDR     0x12
#define DCR_EBC0_CFGDATA     0x13
#define DCR_CPC0_CR0         0xB1
#define DCR_CPC0_CR1         0xB2
#define DCR_CPC0_ECR         0xAA
#define DCR_CPC0_ECID0       0xA8     // 64 bit unique chip serial number
#define DCR_CPC0_ECID1       0xA9     // 64 bit unique chip serial number

// External bus controller (indirect via EBC0_CFGADDR/EBC0_CFGDATA)
#define DCR_EBC0_B0CR        0x00
#define DCR_EBC0_B1CR        0x01
#define DCR_EBC0_B2CR        0x02
#define DCR_EBC0_B3CR        0x03
#define DCR_EBC0_B4CR        0x04
#define DCR_EBC0_B5CR        0x05
#define DCR_EBC0_B6CR        0x06
#define DCR_EBC0_B7CR        0x07
#define DCR_EBC0_B0AP        0x10
#define DCR_EBC0_B1AP        0x11
#define DCR_EBC0_B2AP        0x12
#define DCR_EBC0_B3AP        0x13
#define DCR_EBC0_B4AP        0x14
#define DCR_EBC0_B5AP        0x15
#define DCR_EBC0_B6AP        0x16
#define DCR_EBC0_B7AP        0x17
#define DCR_EBC0_BEAR        0x20
#define DCR_EBC0_BESR0       0x21
#define DCR_EBC0_BESR1       0x22
#define DCR_EBC0_CFG         0x23

// SDRAM controller
#define DCR_SDRAM0_CFG       0x20     // Memory controller options
#define DCR_SDRAM0_STATUS    0x24     // Controller status
#define DCR_SDRAM0_RTR       0x30     // Refresh timer
#define DCR_SDRAM0_PMIT      0x34     // Power management idle timer
#define DCR_SDRAM0_B0CR      0x40     // Bank 0 configuration
#define DCR_SDRAM0_B1CR      0x44     // Bank 1 configuration
#define DCR_SDRAM0_TR        0x80     // Timing

// On-chip memory
#define DCR_OCM0_ISARC       0x18     // Instruction side address compare
#define DCR_OCM0_ISCNTL      0x19     // Instruction side control
#define DCR_OCM0_DSARC       0x1A     // Data side address compare
#define DCR_OCM0_DSCNTL      0x1B     // Data side control