quicc2_diag.c

来自「eCos操作系统源码」· C语言 代码 · 共 1,130 行 · 第 1/4 页

/*    while(1); */

    InitSCC1Uart();

}

/*---------------------------------------------------------------------------
*
* FUNCTION NAME:  InitBDs
*
*
* DESCRIPTION:
*
*  Initializes BD rings to point RX BDs to first half of buffer pool and TX 
*  BDs to second half of buffer pool. This function also initializes the 
*  buffer descriptors control and data length fields. It also ensures that 
*  transmit and recieve functions are disabled before buffer descriptors are
*  initialized.
*
* EXTERNAL EFFECTS: Disable Tx/Rx functions. Changes BDs in dual port ram.
*
* PARAMETERS: None
*
* RETURNS: None
*
*---------------------------------------------------------------------------*/

void InitBDs()

{
   
   /*--------------------------------------------------------------------*/
   /* First let's ensure the SCC1 functions are off while we program the */
   /* buffer descriptors and the parameter ram. Clear the ENT/ENR bits   */
   /* in the GSMR -- disable Transmit/Receive                            */
   /*--------------------------------------------------------------------*/
   
   IMM->scc_regs[SCC1].gsmr_l &= DISABLE_TX_RX;

   /*--------------------------------------*/
   /* Issue Init Stop TX Command for SCC1. */
   /*--------------------------------------*/

   while ((IMM->cpm_cpcr & CPCR_FLG) != READY_TO_RX_CMD); 

   IMM->cpm_cpcr = SCC1_PAGE_SUBBLOCK |
                   CPCR_STOP_TX |
                   CPCR_FLG;             /* ISSUE COMMAND */

   while ((IMM->cpm_cpcr & CPCR_FLG) != READY_TO_RX_CMD); 


   /*-----------------------------------*/
   /* Setup Receiver Buffer Descriptors */
   /*-----------------------------------*/
   
#if defined(CYGDBG_HAL_DEBUG_GDB_BREAK_SUPPORT) \
    || defined(CYGDBG_HAL_DEBUG_GDB_CTRLC_SUPPORT)
   /* Set receive Buffer to generate an interrupt when buffer full */
   RxTxBD->RxBD.bd_cstatus = 0xB000; /* 0xB000; */
#else
   RxTxBD->RxBD.bd_cstatus = 0xA000;     /* Empty, Wrap Bit */
#endif
   //dbg_values[3] = RxTxBD->RxBD.bd_cstatus;
   RxTxBD->RxBD.bd_length = 1;
   RxTxBD->RxBD.bd_addr = &(SCC1Buffers->RxBuffer);

   /*--------------------------------------*/
   /* Setup Transmitter Buffer Descriptors */
   /*--------------------------------------*/

   RxTxBD->TxBD.bd_cstatus = 0x2800;   /* Buffer not yet ready; Wrap Bit 
                                          Clear-to-send_report           */

   RxTxBD->TxBD.bd_length = 1;
   RxTxBD->TxBD.bd_addr = &(SCC1Buffers->TxBuffer);

} /* end InitBDs */


/*---------------------------------------------------------------------------
*
* FUNCTION NAME:  InitSCC1Uart 
*                  
*
* DESCRIPTION:
*
*  SCC1 Uart Mode Initialization Routine.
*                 
* EXTERNAL EFFECT:
*
*  Initializes SCC1 to operate in Uart mode at 9600 Baud, No Parity, 8 data
*  bits, and 1 stop bit. 
*
* PARAMETERS: None
*
* RETURNS: None 
*
*--------------------------------------------------------------------------*/

void InitSCC1Uart()

{
    cyg_uint32 regval;
   /*----------------------------------------------------------------------*/
   /* Configure the parallel ports so that TXD and RXD are connected to    */
   /* the appropriate port pins and are configured according to their      */
   /* functions.                                                           */
   /*----------------------------------------------------------------------*/

   InitParallelPorts();

   /*------------------------------------------*/
   /* Configure Clock Source and Clock Routing */
   /*------------------------------------------*/

   ConfigSCC1Clock();

   /*-----------------------------------*/
   /* Initialize the Buffer Descriptors */
   /*-----------------------------------*/

   InitBDs();

   /*----------------------------------------------------------------------*/
   /* Program Rx and Tx Function Codes (RFCRx/TFCRx).                      */
   /*                                                                      */
   /* - Bits 0-1 reserved. Set to zero.                                    */
   /*                                                                      */
   /* - GBL (Global) = 0 = Snooping Disabled.                              */
   /*                                                                      */
   /* - BO (Byte Ordering) = 11 = Big-endian or true little-endian.        */
   /*                                                                      */
   /* - TC[2] (Transfer Code) = 0 = Transfer code is 0                     */
   /*                                                                      */
   /* - DTB (Data Bus Indicator) = 1 =                                     */
   /*                                                                      */
   /*    Use the Local Bus for SDMA operation. In this example it doesn't  */
   /*    matter because the buffer were located in parameter ram. Normally */
   /*    this bit would be set because data buffers normally will reside   */
   /*    in Local memory.                                                  */
   /*----------------------------------------------------------------------*/

   IMM->pram.serials.scc_pram[SCC1].rfcr = 0x18;

   IMM->pram.serials.scc_pram[SCC1].tfcr = 0x18;

   IMM->scc_regs[SCC1].psmr = 0xB000;

   /*------------------------------------------------------------*/
   /* Set RBASE, TBASE -- Rx,Tx Buffer Descriptor Base Addresses */
   /*------------------------------------------------------------*/

   IMM->pram.serials.scc_pram[SCC1].rbase = (CYG_WORD16)&RxTxBD->RxBD;

   IMM->pram.serials.scc_pram[SCC1].tbase = (CYG_WORD16)&RxTxBD->TxBD;     

   /*-----------------------------------------*/
   /* Set MRBLR -- Max. Receive Buffer Length */
   /*-----------------------------------------*/

   IMM->pram.serials.scc_pram[SCC1].mrblr = 1;
   
   /*----------------------------------------------------------------------*/
   /* Program the General SCC Mode Register High (GSMR_H)                  */
   /*                                                                      */
   /* - Bits 0-14 Reserved. Set to 0.                                      */
   /*                                                                      */
   /* - GDE (Glitch Detect Enable) = 0 = No Glitch Detect. BRG supplies    */
   /*                                    the clock so there's no need to   */
   /*                                    detect glitches.                  */
   /*                                                                      */
   /* - TCRC (Transparent CRC) = 00 = This field is ignored for Uart mode. */
   /*                                                                      */
   /* - REVD (Reverse Data) = 0 = This field is ignored for Uart mode.     */
   /*                                                                      */
   /* - TRX,TTX (Transparent Receiver/Transmitter) = 00 = Normal operation */
   /*                                                                      */
   /* - CDP,CTSP (CD/ & CTS/ sampling) = 00 = Normal Operation (envelope   */
   /*                                         mode.                        */
   /*                                                                      */
   /* - CDS,CTSS (CD/ & CTSS Sampling) = 00 =                              */
   /*                                                                      */
   /*    CD/ or CTS/ is assumed to be asynchronous with data. It is        */
   /*    internally synchronized by the SCC, then data is received (CD/)   */
   /*    or sent (CTS/) after several clock delays.                        */
   /*                                                                      */
   /* - TFL (Transmit FIFO length) = 0 =                                   */
   /*                                                                      */
   /*    Normal Operation. The SCC transmit FIFO is 32 bytes.              */
   /*                                                                      */
   /* - RFW (Rx FIFO Width) = 1 =                                          */
   /*                                                                      */
   /*    Low-latency operation.The receive FIFO is 8 bits wide, reducing   */
   /*    the Rx FIFO to a quarter of it's normal size. This allows data to */
   /*    be written to the buffer as soon as a character is received,      */
   /*    instead of waiting to receive 32 bits. This configuration must be */
   /*    chosen for character-oriented protocols, such as UART. It can     */
   /*    also be used for low-performance, low-latency, transparent        */
   /*    operation.                                                        */
   /*                                                                      */
   /* - TXSY (Trasnmitter Synchronized) = 0 =                              */
   /*                                                                      */
   /*    No synchronization between receiver and transmitter.              */
   /*                                                                      */
   /* - SYNL (Sync Length) = 0 = An external sync (CD/) is used instead of */
   /*                            the sync pattern in the DSR.              */
   /*                                                                      */
   /* - RTSM (RTS/ Mode) = 0 = Send idles between frames as defined by the */
   /*                          protocol and the TEND bit. TRS/ is negated  */
   /*                          between frames.                             */
   /*                                                                      */
   /* - RSYN (Receive Synchronization Timing) = 0 = This field is ignored  */
   /*                                               for Uart mode.         */
   /*                                                                      */
   /*----------------------------------------------------------------------*/
      
   IMM->scc_regs[SCC1].gsmr_h = 0x00000060;


   /*----------------------------------------------------------------------*/
   /* Program the General SCC Mode Register High (GSMR_L)                  */
   /*                                                                      */
   /* - Bit 0 Reserved. Set to 0.                                          */
   /*                                                                      */
   /* - EDGE (Clock Edge) = 00 = Ignored in Uart Mode.                     */
   /*                                                                      */
   /* - TCI (Transmit Clock Invert) = 0 = Normal Operation                 */
   /*                                                                      */
   /* - TSNC (Transmit Sense) = 00 = Infinite. Carrier sense is always     */
   /*                                active.                               */
   /*                                                                      */
   /* - RINV (DPLL Rx Input Invert) = 0 = Do not invert.                   */
   /*                                                                      */
   /* - TINV (DPLL Tx Input Invert) = 0 = Do not invert.                   */
   /*                                                                      */
   /* - TPL (Tx Preamble Length) = 000 = No Preamble.                      */
   /*                                                                      */
   /* - TPP (Tx Preamble Pattern) = 00 = All zeros. This field is ignored  */
   /*                                    for Uart mode.                    */
   /*                                                                      */
   /* - TEND (Transmitter Frame Ending) = 0 =                              */
   /*                                                                      */
   /*    Default operation. TxD is encoded only when data is sent,         */
   /*    including the preamble and opening and closing flags/syncs. When  */
   /*    no data is available to send, the signal is driven high.          */
   /*                                                                      */
   /* - TDCR (Transmitter DPLL Clock Rate) = 10 =                          */
   /*                                                                      */
   /*    16x clock mode. This value is normally chosen for Uart mode.      */
   /*                                                                      */
   /* - RDCR (Receiver DPLL Clock Rate) = 10 =                             */
   /*                                                                      */
   /*    16x clock mode. This value is normally chosen for Uart mode.      */
   /*                                                                      */
   /* - RENC (Receiver Decoding Method) = 000 =                            */
   /*                                                                      */
   /*    NRZ. Required for Uart Mode (asynchronous or synchronous).        */
   /*                                                                      */
   /* - TENC (Transmitter Encoding Method) = 000 =                         */
   /*                                                                      */
   /*    NRZ. Required for Uart Mode (asynchronous or synchronous).        */
   /*                                                                      */
   /* - DIAG (Diagnostic Mode) = 01 = Loopback                             */
   /*                                                                      */
   /* - ENR (Enable Receiver) = 0 = Disabled for now. Will enabled later in*/
   /*                               this function.                         */
   /*                                                                      */
   /* - ENT (Enable Transmitter) = 0 = Disabled for now. Will enable later */
   /*                                  in this function.                   */
   /*                                                                      */
   /* - MODE (Channel Protocol Mode) = 0100 = Uart mode.                   */
   /*                                                                      */
   /*----------------------------------------------------------------------*/


   IMM->scc_regs[SCC1].gsmr_l = 0x00028004;  

   /*-----------------------------------------*/
   /* Clear SCCE Register by writing all 1's. */
   /*-----------------------------------------*/

   IMM->scc_regs[SCC1].scce = ALL_ONES;