mpc8260.h
来自「eCos操作系统源码」· C头文件 代码 · 共 1,235 行 · 第 1/4 页
H
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volatile CYG_BYTE reserved38[0x4]; /* Reserved area */ volatile CYG_WORD clocks_scmr; /* System Clock Mode Register */ volatile CYG_BYTE reserved39[0x4]; /* Reserved area */ volatile CYG_WORD clocks_rsr; /* Reset Status Register */ volatile CYG_WORD clocks_rmr; /* Reset Moode Register */ volatile CYG_BYTE reserved40[0x68]; /* Reserved area *//* io_ports */ struct io_regs { volatile CYG_WORD pdir; /* Port A-D Data Direction Register */ volatile CYG_WORD ppar; /* Port A-D Pin Assignment Register */ volatile CYG_WORD psor; /* Port A-D Special Operation Register */ volatile CYG_WORD podr; /* Port A-D Open Drain Register */ volatile CYG_WORD pdat; /* Port A-D Data Register */ volatile CYG_BYTE reserved41[0xc]; /* Reserved area */ } io_regs[4];/* cpm_timers */ volatile CYG_BYTE cpm_timers_tgcr1; /* Timer Global Configuration Register */ volatile CYG_BYTE reserved42[0x3]; /* Reserved area */ volatile CYG_BYTE cpm_timers_tgcr2; /* Timer Global Configuration Register */ volatile CYG_BYTE reserved43[0xb]; /* Reserved area */ volatile CYG_WORD16 cpm_timers_tmr1; /* Timer Mode Register */ volatile CYG_WORD16 cpm_timers_tmr2; /* Timer Mode Register */ volatile CYG_WORD16 cpm_timers_trr1; /* Timer Reference Register */ volatile CYG_WORD16 cpm_timers_trr2; /* Timer Reference Register */ volatile CYG_WORD16 cpm_timers_tcr1; /* Timer Capture Register */ volatile CYG_WORD16 cpm_timers_tcr2; /* Timer Capture Register */ volatile CYG_WORD16 cpm_timers_tcn1; /* Timer Counter */ volatile CYG_WORD16 cpm_timers_tcn2; /* Timer Counter */ volatile CYG_WORD16 cpm_timers_tmr3; /* Timer Mode Register */ volatile CYG_WORD16 cpm_timers_tmr4; /* Timer Mode Register */ volatile CYG_WORD16 cpm_timers_trr3; /* Timer Reference Register */ volatile CYG_WORD16 cpm_timers_trr4; /* Timer Reference Register */ volatile CYG_WORD16 cpm_timers_tcr3; /* Timer Capture Register */ volatile CYG_WORD16 cpm_timers_tcr4; /* Timer Capture Register */ volatile CYG_WORD16 cpm_timers_tcn3; /* Timer Counter */ volatile CYG_WORD16 cpm_timers_tcn4; /* Timer Counter */ volatile CYG_WORD16 cpm_timers_ter[4]; /* Timer Event Register */ volatile CYG_BYTE reserved44[0x260]; /* Reserved area *//* sdma general */ volatile CYG_BYTE sdma_sdsr; /* SDMA Status Register */ volatile CYG_BYTE reserved45[0x3]; /* Reserved area */ volatile CYG_BYTE sdma_sdmr; /* SDMA Mask Register */ volatile CYG_BYTE reserved46[0x3]; /* Reserved area *//* idma */ volatile CYG_BYTE idma_idsr1; /* IDMA Status Register */ volatile CYG_BYTE reserved47[0x3]; /* Reserved area */ volatile CYG_BYTE idma_idmr1; /* IDMA Mask Register */ volatile CYG_BYTE reserved48[0x3]; /* Reserved area */ volatile CYG_BYTE idma_idsr2; /* IDMA Status Register */ volatile CYG_BYTE reserved49[0x3]; /* Reserved area */ volatile CYG_BYTE idma_idmr2; /* IDMA Mask Register */ volatile CYG_BYTE reserved50[0x3]; /* Reserved area */ volatile CYG_BYTE idma_idsr3; /* IDMA Status Register */ volatile CYG_BYTE reserved51[0x3]; /* Reserved area */ volatile CYG_BYTE idma_idmr3; /* IDMA Mask Register */ volatile CYG_BYTE reserved52[0x3]; /* Reserved area */ volatile CYG_BYTE idma_idsr4; /* IDMA Status Register */ volatile CYG_BYTE reserved53[0x3]; /* Reserved area */ volatile CYG_BYTE idma_idmr4; /* IDMA Mask Register */ volatile CYG_BYTE reserved54[0x2c3]; /* Reserved area */ /* fcc */ struct fcc_regs { volatile CYG_WORD fcc_gfmr; /* FCC General Mode Register */ volatile CYG_WORD fcc_psmr; /* FCC Protocol Specific Mode Register */ volatile CYG_WORD16 fcc_todr; /* FCC Transmit On Demand Register */ volatile CYG_BYTE reserved55[0x2]; /* Reserved area */ volatile CYG_WORD16 fcc_dsr; /* FCC Data Sync. Register */ volatile CYG_BYTE reserved56[0x2]; /* Reserved area */ volatile CYG_WORD fcc_fcce; /* FCC Event Register */ volatile CYG_WORD fcc_fccm; /* FCC Mask Register */ volatile CYG_BYTE fcc_fccs; /* FCC Status Register */ volatile CYG_BYTE reserved57[0x3]; /* Reserved area */ volatile CYG_WORD fcc_ftprr; /* FCC Transmit Partial Rate Register */ } fcc_regs[3]; volatile CYG_BYTE reserved58[0x290]; /* Reserved area */ /* brgs 5 through 8 */ volatile CYG_WORD brgs_brgc5; /* Baud Rate Generator 5 Config Register */ volatile CYG_WORD brgs_brgc6; /* Baud Rate Generator 6 Config Register */ volatile CYG_WORD brgs_brgc7; /* Baud Rate Generator 7 Config Register */ volatile CYG_WORD brgs_brgc8; /* Baud Rate Generator 8 Config Register */ volatile CYG_BYTE reserved59[0x260]; /* Reserved area */ /* i2c */ volatile CYG_BYTE i2c_i2mod; /* IC Mode Register */ volatile CYG_BYTE reserved60[0x3]; /* Reserved area */ volatile CYG_BYTE i2c_i2add; /* IC Address Register */ volatile CYG_BYTE reserved61[0x3]; /* Reserved area */ volatile CYG_BYTE i2c_i2brg; /* IC BRG Register */ volatile CYG_BYTE reserved62[0x3]; /* Reserved area */ volatile CYG_BYTE i2c_i2com; /* IC Command Register */ volatile CYG_BYTE reserved63[0x3]; /* Reserved area */ volatile CYG_BYTE i2c_i2cer; /* IC Event Register */ volatile CYG_BYTE reserved64[0x3]; /* Reserved area */ volatile CYG_BYTE i2c_i2cmr; /* IC Mask Register */ volatile CYG_BYTE reserved65[0x14b]; /* Reserved area */ /* cpm */ volatile CYG_WORD cpm_cpcr; /* Communication Processor Command Register */ volatile CYG_WORD cpm_rccr; /* RISC Configuration Register */ volatile CYG_WORD cpm_rmdr; /* RISC Microcode Dev. Support Control Reg. */ volatile CYG_WORD16 cpm_rctr1; /* RISC Controller Trap Register */ volatile CYG_WORD16 cpm_rctr2; /* RISC Controller Trap Register */ volatile CYG_WORD16 cpm_rctr3; /* RISC Controller Trap Register */ volatile CYG_WORD16 cpm_rctr4; /* RISC Controller Trap Register */ volatile CYG_BYTE reserved66[0x2]; /* Reserved area */ volatile CYG_WORD16 cpm_rter; /* RISC Timers Event Register */ volatile CYG_BYTE reserved67[0x2]; /* Reserved area */ volatile CYG_WORD16 cpm_rtmr; /* RISC Timers Mask Register */ volatile CYG_WORD16 cpm_rtscr; /* RISC Time-Stamp Timer Control Register */ volatile CYG_WORD16 cpm_rmds; /* RISC Development Support Status Register */ volatile CYG_WORD cpm_rtsr; /* RISC Time-Stamp Register */ volatile CYG_BYTE reserved68[0xc]; /* Reserved area *//* brgs 1 through 4 */ volatile CYG_WORD brgs_brgc1; /* Baud Rate Generator 5 Config Register */ volatile CYG_WORD brgs_brgc2; /* Baud Rate Generator 2 Config Register */ volatile CYG_WORD brgs_brgc3; /* Baud Rate Generator 3 Config Register */ volatile CYG_WORD brgs_brgc4; /* Baud Rate Generator 4 Config Register */ /* scc */ struct scc_regs_8260 { volatile CYG_WORD gsmr_l; /* SCC General Mode Register */ volatile CYG_WORD gsmr_h; /* SCC General Mode Register */ volatile CYG_WORD16 psmr; /* SCC Protocol Specific Mode Register */ volatile CYG_BYTE reserved69[0x2]; /* Reserved area */ volatile CYG_WORD16 todr; /* SCC Transmit-On-Demand Register */ volatile CYG_WORD16 dsr; /* SCC Data Synchronization Register */ volatile CYG_WORD16 scce; /* SCC Event Register */ volatile CYG_BYTE reserved70[0x2]; /* Reserved area */ volatile CYG_WORD16 sccm; /* SCC Mask Register */ volatile CYG_BYTE reserved71; /* Reserved area */ volatile CYG_BYTE sccs; /* SCC Status Register */ volatile CYG_BYTE reserved72[0x8]; /* Reserved area */ } scc_regs[4]; /* smc */ struct smc_regs_8260 { volatile CYG_BYTE reserved73[0x2]; /* Reserved area */ volatile CYG_WORD16 smc_smcmr; /* SMC Mode Register */ volatile CYG_BYTE reserved74[0x2]; /* Reserved area */ volatile CYG_BYTE smc_smce; /* SMC Event Register */ volatile CYG_BYTE reserved75[0x3]; /* Reserved area */ volatile CYG_BYTE smc_smcm; /* SMC Mask Register */ volatile CYG_BYTE reserved76[0x5]; /* Reserved area */ } smc_regs[2]; /* spi */ volatile CYG_WORD16 spi_spmode; /* SPI Mode Register */ volatile CYG_BYTE reserved77[0x4]; /* Reserved area */ volatile CYG_BYTE spi_spie; /* SPI Event Register */ volatile CYG_BYTE reserved78[0x3]; /* Reserved area */ volatile CYG_BYTE spi_spim; /* SPI Mask Register */ volatile CYG_BYTE reserved79[0x2]; /* Reserved area */ volatile CYG_BYTE spi_spcom; /* SPI Command Register */ volatile CYG_BYTE reserved80[0x52]; /* Reserved area */ /* cpm_mux */ volatile CYG_BYTE cpm_mux_cmxsi1cr; /* CPM MUX SI Clock Route Register */ volatile CYG_BYTE reserved81; /* Reserved area */ volatile CYG_BYTE cpm_mux_cmxsi2cr; /* CPM MUX SI Clock Route Register */ volatile CYG_BYTE reserved82; /* Reserved area */ volatile CYG_WORD cpm_mux_cmxfcr; /* CPM MUX FCC Clock Route Register */ volatile CYG_WORD cpm_mux_cmxscr; /* CPM MUX SCC Clock Route Register */ volatile CYG_BYTE cpm_mux_cmxsmr; /* CPM MUX SMC Clock Route Register */ volatile CYG_BYTE reserved83; /* Reserved area */ volatile CYG_WORD16 cpm_mux_cmxuar; /* CPM MUX UTOPIA Address Register */ volatile CYG_BYTE reserved84[0x10]; /* Reserved area */ /* si */ struct si_regs { volatile CYG_WORD16 si_si1mr[4]; /* SI TDM Mode Registers */ volatile CYG_BYTE si_si1gmr; /* SI Global Mode Register */ volatile CYG_BYTE reserved85; /* Reserved area */ volatile CYG_BYTE si_si1cmdr; /* SI Command Register */ volatile CYG_BYTE reserved86; /* Reserved area */ volatile CYG_BYTE si_si1str; /* SI Status Register */ volatile CYG_BYTE reserved87; /* Reserved area */ volatile CYG_WORD16 si_si1rsr; /* SI RAM Shadow Address Register */ volatile CYG_WORD16 mcc_mcce; /* MCC Event Register */ volatile CYG_BYTE reserved88[0x2]; /* Reserved area */ volatile CYG_WORD16 mcc_mccm; /* MCC Mask Register */ volatile CYG_BYTE reserved89[0x2]; /* Reserved area */ volatile CYG_BYTE mcc_mccf; /* MCC Configuration Register */ volatile CYG_BYTE reserved90[0x7]; /* Reserved area */ } si_regs[2]; volatile CYG_BYTE reserved91[0x4a0]; /* Reserved area */ /* si_ram */ struct si_ram { CYG_WORD16 si1_ram_si1_tx_ram[0x100]; /* SI Transmit Routing RAM */ volatile CYG_BYTE reserved92[0x200]; /* Reserved area */ CYG_WORD16 si1_ram_si1_rx_ram[0x100]; /* SI Receive Routing RAM */ volatile CYG_BYTE reserved93[0x200]; /* Reserved area */ } si_ram[2]; volatile CYG_BYTE reserved94[0x1000]; /* Reserved area */} _PackedType t_PQ2IMM;/***************************************************************************//* General Global Definitions *//***************************************************************************/#define PAGE1 0 /* SCC1 Index into SCC Param RAM Array */#define PAGE2 1 /* SCC2 Index into SCC Param RAM Array */#define PAGE3 2 /* SCC3 Index into SCC Param RAM Array */#define PAGE4 3 /* SCC4 Index into SCC Param RAM Array */#define SCC1 0 /* SCC1 Index into SCC Regs Array */ #define SCC2 1 /* SCC2 Index into SCC Regs Array */ #define SCC3 2 /* SCC3 Index into SCC Regs Array */ #define SCC4 3 /* SCC4 Index into SCC Regs Array */ #define SMC1 0 /* SMC1 Index into SMC Regs Array */ #define SMC2 1 /* SMC2 Index into SMC Regs Array */ #define PORT_A 0 /* Parallel port A registers */#define PORT_B 1 /* Parallel port B registers */#define PORT_C 2 /* Parallel port C registers */#define PORT_D 3 /* Parallel port D registers *//*--------------------------------*//* KEEP ALIVE POWER REGISTERS KEY *//*--------------------------------*/#define KEEP_ALIVE_KEY 0x55ccaa33/*------------------------------------------** CPM Command Register (CPCR) **-------------------------------------------** NOTE: This register is cleared by reset. ** See MPC8260 User's Manual. **-------------------------------------------*/#define CPCR_RST 0x80000000 /* Software Reset Command */#define CPCR_FLG 0x00010000 /* Command Semaphore Flag *//*-----------------------------------------------*//* Definitions for SCC CPCR Subblock/Page codes. *//*-----------------------------------------------*/#define SCC1_PAGE_SUBBLOCK 0x00800000 /* page 0, code = 4 */#define SCC2_PAGE_SUBBLOCK 0x04A00000 /* page 1, code = 5 */#define SCC3_PAGE_SUBBLOCK 0x08C00000 /* page 2, code = 6 */#define SCC4_PAGE_SUBBLOCK 0x0CE00000 /* page 3, code = 7 *//*-----------------------------------------------*//* Definitions for SMC CPCR Subblock/Page codes. *//*-----------------------------------------------*/#define SMC1_PAGE_SUBBLOCK 0x1D000000 /* page 7, code = 8 */#define SMC2_PAGE_SUBBLOCK 0x21200000 /* page 8, code = 9 *//*-----------------------------*//* Opcode definitions for SCCs, opcodes for SMC's are the same * except not all codes are valid for SMC *//*-----------------------------*/#define CPCR_INIT_TX_RX_PARAMS 0x00000000 /* Opcode 0 */#define CPCR_INIT_RX_PARAMS 0x00000001 /* Opcode 1 */#define CPCR_INIT_TX_PARAMS 0x00000002 /* Opcode 2 */#define CPCR_ENTER_HUNT_MODE 0x00000003 /* Opcode 3 */#define CPCR_STOP_TX 0x00000004 /* Opcode 4 */#define CPCR_GRACEFUL_STOP_TX 0x00000005 /* Opcode 5 */#define CPCR_RESTART_TX 0x00000006 /* Opcode 6 */#define CPCR_CLOSE_RX_BD 0x00000007 /* Opcode 7 */#define CPCR_SET_GRP_ADDR 0x00000008 /* Opcode 8 */#define CPCR_RESET_BCS 0x0000000A /* Opcode 10 *//*-----------------------------------------------------*//* General Definitions for SCC CPCR Command Operations *//*-----------------------------------------------------*/#define READY_TO_RX_CMD 0x00000000/*-------------------------*//* General SCC Definitions *//*-------------------------*/#define DISABLE_TX_RX 0xFFFFFFCF /* Clear the ENT/ENR bits in the GSMR Disables the transmit & Receive port */#define GSMR_L1_ENT 0x00000010 /* ENT bit for the GSMR low register */#define GSMR_L1_ENR 0x00000020 /* ENR bit for the GSMR low register */#define ALL_ONES 0xFFFF#endif // ifndef CYGONCE_HAL_PPC_QUICC2_MPC8260_H⌨️ 快捷键说明
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