mpc8260.h
来自「eCos操作系统源码」· C头文件 代码 · 共 1,235 行 · 第 1/4 页
H
1,235 行
CYG_WORD16 mrblr; /* Rx buffer length */ CYG_WORD rstate; /* Rx internal state */ CYG_WORD rptr; /* Rx internal data pointer */ CYG_WORD16 rbptr; /* rb BD Pointer */ CYG_WORD16 rcount; /* Rx internal byte count */ CYG_WORD rtemp; /* Rx temp */ CYG_WORD tstate; /* Tx internal state */ CYG_WORD tptr; /* Tx internal data pointer */ CYG_WORD16 tbptr; /* Tx BD pointer */ CYG_WORD16 tcount; /* Tx byte count */ CYG_WORD ttemp; /* Tx temp */ /* SMC UART-specific PRAM */ CYG_WORD16 max_idl; /* Maximum IDLE Characters */ CYG_WORD16 idlc; /* Temporary IDLE Counter */ CYG_WORD16 brkln; /* Last Rx Break Length */ CYG_WORD16 brkec; /* Rx Break Condition Counter */ CYG_WORD16 brkcr; /* Break Count Register (Tx) */ CYG_WORD16 r_mask; /* Temporary bit mask */ } _PackedType t_Smc_Pram;/*---------------------------------------------------------------------------*//* IDMA PARAMETER RAM *//*---------------------------------------------------------------------------*/typedef _Packed struct { CYG_WORD16 ibase; /* IDMA BD Base Address */ CYG_WORD16 dcm; /* DMA channel mode register */ CYG_WORD16 ibdptr; /* next bd ptr */ CYG_WORD16 DPR_buf; /* ptr to internal 64 byte buffer */ CYG_WORD16 BUF_inv; /* The quantity of data in DPR_buf */ CYG_WORD16 SS_max; /* Steady State Max. transfer size */ CYG_WORD16 DPR_in_ptr; /* write ptr for the internal buffer */ CYG_WORD16 sts; /* Source Transfer Size */ CYG_WORD16 DPR_out_ptr; /* read ptr for the internal buffer */ CYG_WORD16 seob; /* Source end of burst */ CYG_WORD16 deob; /* Destination end of burst */ CYG_WORD16 dts; /* Destination Transfer Size */ CYG_WORD16 RetAdd; /* return address when ERM==1 */ CYG_WORD16 Reserved; /* reserved */ CYG_WORD BD_cnt; /* Internal byte count */ CYG_WORD S_ptr; /* source internal data ptr */ CYG_WORD D_ptr; /* destination internal data ptr */ CYG_WORD istate; /* Internal state */} _PackedType t_Idma_Pram;/*-------------------------------------------------------------------*//* INTER-INTEGRATED CIRCUIT (I2C) *//*-------------------------------------------------------------------*/typedef _Packed struct { CYG_WORD16 rbase; /* RX BD base address */ CYG_WORD16 tbase; /* TX BD base address */ CYG_BYTE rfcr; /* Rx function code */ CYG_BYTE tfcr; /* Tx function code */ CYG_WORD16 mrblr; /* Rx buffer length */ CYG_WORD rstate; /* Rx internal state */ CYG_WORD rptr; /* Rx internal data pointer */ CYG_WORD16 rbptr; /* rb BD Pointer */ CYG_WORD16 rcount; /* Rx internal byte count */ CYG_WORD rtemp; /* Rx temp */ CYG_WORD tstate; /* Tx internal state */ CYG_WORD tptr; /* Tx internal data pointer */ CYG_WORD16 tbptr; /* Tx BD pointer */ CYG_WORD16 tcount; /* Tx byte count */ CYG_WORD ttemp; /* Tx temp */} _PackedType t_I2c_Pram;/*---------------------------------------------------------------------------*//* SERIAL PERIPHERAL INTERFACE (SPI) *//*---------------------------------------------------------------------------*/typedef _Packed struct { CYG_WORD16 rbase; /* Rx BD Base Address */ CYG_WORD16 tbase; /* Tx BD Base Address */ CYG_BYTE rfcr; /* Rx function code */ CYG_BYTE tfcr; /* Tx function code */ CYG_WORD16 mrblr; /* Rx buffer length */ CYG_WORD rstate; /* Rx internal state */ CYG_WORD rptr; /* Rx internal data pointer */ CYG_WORD16 rbptr; /* Rx BD Pointer */ CYG_WORD16 rcount; /* Rx internal byte count */ CYG_WORD rtemp; /* Rx temp */ CYG_WORD tstate; /* Tx internal state */ CYG_WORD tptr; /* Tx internal data pointer */ CYG_WORD16 tbptr; /* Tx BD pointer */ CYG_WORD16 tcount; /* Tx byte count */ CYG_WORD ttemp; /* Tx temp */ CYG_BYTE reserved[8];} _PackedType t_Spi_Pram;/*---------------------------------------------------------------------------*//* RISC TIMER PARAMETER RAM *//*---------------------------------------------------------------------------*/typedef _Packed struct { CYG_WORD16 tm_base; /* RISC timer table base adr */ CYG_WORD16 tm_ptr; /* RISC timer table pointer */ CYG_WORD16 r_tmr; /* RISC timer mode register */ CYG_WORD16 r_tmv; /* RISC timer valid register */ CYG_WORD tm_cmd; /* RISC timer cmd register */ CYG_WORD tm_cnt; /* RISC timer internal cnt */} _PackedType t_timer_pram;/*--------------------------------------------------------------------------*//* ROM MICROCODE PARAMETER RAM AREA *//*--------------------------------------------------------------------------*/typedef _Packed struct { CYG_WORD16 rev_num; /* Ucode Revision Number */ CYG_WORD16 d_ptr; /* MISC Dump area pointer */} _PackedType t_ucode_pram;/*--------------------------------------------------------------------------*//* MAIN DEFINITION OF MPC8260 INTERNAL MEMORY MAP *//*--------------------------------------------------------------------------*/typedef _Packed struct {/* cpm_ram */ t_Mch_Pram mch_pram[256]; /* MCC logical channels parameter ram */ volatile CYG_BYTE reserved0[0x4000]; /* Reserved area */ /* DPR_BASE+0x8000*/ union { /*for access to the PRAM structs for SCCs, FCCs, and MCCs */ struct serials { t_Scc_Pram scc_pram[4]; t_Fcc_Pram fcc_pram[3]; t_Mcc_Pram mcc_pram[2]; volatile CYG_BYTE reserved1[0x700]; } serials; /* for access to ATM PRAM structs */ struct atm { volatile CYG_BYTE reserved2[0x400]; t_Atm_Pram atm_pram[2]; volatile CYG_BYTE reserved3[0xa00]; } atm; /* for access to the memory locations holding user-defined base addresses of PRAM for SMCs, IDMA, SPI, and I2C. */ struct standard { volatile CYG_BYTE scc1[0x100]; volatile CYG_BYTE scc2[0x100]; volatile CYG_BYTE scc3[0x100]; volatile CYG_BYTE scc4[0x100]; volatile CYG_BYTE fcc1[0x100]; volatile CYG_BYTE fcc2[0x100]; volatile CYG_BYTE fcc3[0x100]; volatile CYG_BYTE mcc1[0x80]; volatile CYG_BYTE reserved_0[0x7c]; volatile CYG_BYTE smc1[0x2]; volatile CYG_BYTE idma1[0x2]; volatile CYG_BYTE mcc2[0x80]; volatile CYG_BYTE reserved_1[0x7c]; volatile CYG_BYTE smc2[0x2]; volatile CYG_BYTE idma2[0x2]; volatile CYG_BYTE reserved_2[0xfc]; volatile CYG_BYTE spi[0x2]; volatile CYG_BYTE idma3[0x2]; volatile CYG_BYTE reserved_3[0xe0]; volatile CYG_BYTE timers[0x10]; volatile CYG_BYTE Rev_num[0x2]; volatile CYG_BYTE D_ptr[0x2]; volatile CYG_BYTE reserved_4[0x4]; volatile CYG_BYTE rand[0x4]; volatile CYG_BYTE i2c[0x2]; volatile CYG_BYTE idma4[0x2]; volatile CYG_BYTE reserved_5[0x500]; } standard; } pram; volatile CYG_BYTE reserved11[0x2000]; /* Reserved area */ volatile CYG_BYTE cpm_ram_dpram_2[0x1000]; /* Internal RAM */ volatile CYG_BYTE reserved12[0x4000]; /* Reserved area *//* siu */ volatile CYG_WORD siu_siumcr; /* SIU Module Configuration Register */ volatile CYG_WORD siu_sypcr; /* System Protection Control Register */ volatile CYG_BYTE reserved13[0x6]; /* Reserved area */ volatile CYG_WORD16 siu_swsr; /* Software Service Register *//* buses */ volatile CYG_BYTE reserved14[0x14]; /* Reserved area */ volatile CYG_WORD bcr; /* Bus Configuration Register */ volatile CYG_BYTE ppc_acr; /* Arbiter Configuration Register */ volatile CYG_BYTE reserved15[0x3]; /* Reserved area */ volatile CYG_WORD ppc_alrh; /* Arbitration level Register (First clients)*/ volatile CYG_WORD ppc_alrl; /* Arbitration Level Register (Next clients) */ volatile CYG_BYTE lcl_acr; /* LCL Arbiter Configuration Register */ volatile CYG_BYTE reserved16[0x3]; /* Reserved area */ volatile CYG_WORD lcl_alrh; /* LCL Arbitration level Register (First clients)*/ volatile CYG_WORD lcl_alrl; /* LCL Arbitration Level Register (Next clients) */ volatile CYG_WORD tescr1; /* PPC bus transfer error status control register 1 */ volatile CYG_WORD tescr2; /* PPC bus transfer error status control register 2 */ volatile CYG_WORD ltescr1; /* Local bus transfer error status control register 1 */ volatile CYG_WORD ltescr2; /* Local bus transfer error status control register 2 */ volatile CYG_WORD pdtea; /* PPC bus DMA Transfer Error Address */ volatile CYG_BYTE pdtem; /* PPC bus DMA Transfer Error MSNUM */ volatile CYG_BYTE reserved17[0x3]; /* Reserved area */ volatile CYG_WORD ldtea; /* PPC bus DMA Transfer Error Address */ volatile CYG_BYTE ldtem; /* PPC bus DMA Transfer Error MSNUM */ volatile CYG_BYTE reserved18[0xa3]; /* Reserved area *//* memc */ struct mem_regs { volatile CYG_WORD memc_br; /* Base Register */ volatile CYG_WORD memc_or; /* Option Register */ } mem_regs[12]; volatile CYG_BYTE reserved19[0x8]; /* Reserved area */ volatile CYG_WORD memc_mar; /* Memory Address Register */ volatile CYG_BYTE reserved20[0x4]; /* Reserved area */ volatile CYG_WORD memc_mamr; /* Machine A Mode Register */ volatile CYG_WORD memc_mbmr; /* Machine B Mode Register */ volatile CYG_WORD memc_mcmr; /* Machine C Mode Register */ volatile CYG_WORD memc_mdmr; /* Machine D Mode Register */ volatile CYG_BYTE reserved21[0x4]; /* Reserved area */ volatile CYG_WORD16 memc_mptpr; /* Memory Periodic Timer Prescaler */ volatile CYG_BYTE reserved22[0x2]; /* Reserved area */ volatile CYG_WORD memc_mdr; /* Memory Data Register */ volatile CYG_BYTE reserved23[0x4]; /* Reserved area */ volatile CYG_WORD memc_psdmr; /* PowerPC Bus SDRAM machine Mode Register */ volatile CYG_WORD memc_lsdmr; /* Local Bus SDRAM machine Mode Registe */ volatile CYG_BYTE memc_purt; /* PowerPC Bus assigned UPM Refresh Timer */ volatile CYG_BYTE reserved24[0x3]; /* Reserved area */ volatile CYG_BYTE memc_psrt; /* PowerPC BusBus assigned SDRAM Refresh Timer */ volatile CYG_BYTE reserved25[0x3]; /* Reserved area */ volatile CYG_BYTE memc_lurt; /* Local Bus assigned UPM Refresh Timer */ volatile CYG_BYTE reserved26[0x3]; /* Reserved area */ volatile CYG_BYTE memc_lsrt; /* Local Bus assigned SDRAM Refresh Timer */ volatile CYG_BYTE reserved27[0x3]; /* Reserved area */ volatile CYG_WORD memc_immr; /* Internal Memory Map Register *//* pci */ volatile CYG_WORD pcibr0; /* Base address+valid for PCI window 1 */ volatile CYG_WORD pcibr1; /* Base address+valid for PCI window 2 */ volatile CYG_BYTE reserved28[0x10]; /* Reserved area */ volatile CYG_WORD pcimsk0; /* Mask for PCI window 1 */ volatile CYG_WORD pcimsk1; /* Mask for PCI window 2 */ volatile CYG_BYTE reserved29[0x54]; /* Reserved area *//* si_timers */ volatile CYG_WORD16 si_timers_tmcntsc; /* Time Counter Status and Control Register */ volatile CYG_BYTE reserved30[0x2]; /* Reserved area */ volatile CYG_WORD si_timers_tmcnt; /* Time Counter Register */ volatile CYG_WORD si_timers_tmcntsec; /* Time Counter Seconds*/ volatile CYG_WORD si_timers_tmcntal; /* Time Counter Alarm Register */ volatile CYG_BYTE reserved31[0x10]; /* Reserved area */ volatile CYG_WORD16 si_timers_piscr; /* Periodic Interrupt Status and Control Reg. */ volatile CYG_BYTE reserved32[0x2]; /* Reserved area */ volatile CYG_WORD si_timers_pitc; /* Periodic Interrupt Count Register */ volatile CYG_WORD si_timers_pitr; /* Periodic Interrupt Timer Register */ volatile CYG_BYTE reserved33[0x54]; /* Reserved area *//* test module registers */ volatile CYG_WORD tstmhr; volatile CYG_WORD tstmlr; volatile CYG_WORD16 tster; volatile CYG_BYTE reserved34[0x156]; /* Reserved area */ /* pci, part 2 */ volatile CYG_WORD pci_pci; /* PCI Configuration space */ volatile CYG_BYTE reserved35[0x7fc]; /* Reserved area */ /* ic */ volatile CYG_WORD16 ic_sicr; /* Interrupt Configuration Register */ volatile CYG_BYTE reserved36[0x2]; /* Reserved area */ volatile CYG_WORD ic_sivec; /* CP Interrupt Vector Register */ volatile CYG_WORD ic_sipnr_h; /* Interrupt Pending Register (HIGH) */ volatile CYG_WORD ic_sipnr_l; /* Interrupt Pending Register (LOW) */ volatile CYG_WORD ic_siprr; /* SIU Interrupt Priority Register */ volatile CYG_WORD ic_scprr_h; /* Interrupt Priority Register (HIGH) */ volatile CYG_WORD ic_scprr_l; /* Interrupt Priority Register (LOW) */ volatile CYG_WORD ic_simr_h; /* Interrupt Mask Register (HIGH) */ volatile CYG_WORD ic_simr_l; /* Interrupt Mask Register (LOW) */ volatile CYG_WORD ic_siexr; /* External Interrupt Control Register */ volatile CYG_BYTE reserved37[0x58]; /* Reserved area *//* clocks */ volatile CYG_WORD clocks_sccr; /* System Clock Control Register */⌨️ 快捷键说明
复制代码Ctrl + C
搜索代码Ctrl + F
全屏模式F11
增大字号Ctrl + =
减小字号Ctrl + -
显示快捷键?