var_intr.h

来自「eCos操作系统源码」· C头文件 代码 · 共 1,900 行 · 第 1/5 页

        HAL_READ_UINT16(CYGARC_REG_IMM_MIOS1ER0, mios1er0);
        mios1er0 |= (CYGARC_REG_IMM_MIOS1ER0_EN13);
        HAL_WRITE_UINT16(CYGARC_REG_IMM_MIOS1ER0, mios1er0);
        break;
    }

    case CYGNUM_HAL_INTERRUPT_IMB3_MIOS_MDASM14:
    {
        cyg_uint16 mios1er0;

        HAL_READ_UINT16(CYGARC_REG_IMM_MIOS1ER0, mios1er0);
        mios1er0 |= (CYGARC_REG_IMM_MIOS1ER0_EN14);
        HAL_WRITE_UINT16(CYGARC_REG_IMM_MIOS1ER0, mios1er0);
        break;
    }

    case CYGNUM_HAL_INTERRUPT_IMB3_MIOS_MDASM15:
    {
        cyg_uint16 mios1er0;

        HAL_READ_UINT16(CYGARC_REG_IMM_MIOS1ER0, mios1er0);
        mios1er0 |= (CYGARC_REG_IMM_MIOS1ER0_EN15);
        HAL_WRITE_UINT16(CYGARC_REG_IMM_MIOS1ER0, mios1er0);
        break;
    }

    case CYGNUM_HAL_INTERRUPT_IMB3_MIOS_MPWM16:
    {
        cyg_uint16 mios1er1;

        HAL_READ_UINT16(CYGARC_REG_IMM_MIOS1ER1, mios1er1);
        mios1er1 |= (CYGARC_REG_IMM_MIOS1ER1_EN16);
        HAL_WRITE_UINT16(CYGARC_REG_IMM_MIOS1ER1, mios1er1);
        break;
    }

    case CYGNUM_HAL_INTERRUPT_IMB3_MIOS_MPWM17:
    {
        cyg_uint16 mios1er1;

        HAL_READ_UINT16(CYGARC_REG_IMM_MIOS1ER1, mios1er1);
        mios1er1 |= (CYGARC_REG_IMM_MIOS1ER1_EN17);
        HAL_WRITE_UINT16(CYGARC_REG_IMM_MIOS1ER1, mios1er1);
        break;
    }

    case CYGNUM_HAL_INTERRUPT_IMB3_MIOS_MPWM18:
    {
        cyg_uint16 mios1er1;

        HAL_READ_UINT16(CYGARC_REG_IMM_MIOS1ER1, mios1er1);
        mios1er1 |= (CYGARC_REG_IMM_MIOS1ER1_EN18);
        HAL_WRITE_UINT16(CYGARC_REG_IMM_MIOS1ER1, mios1er1);
        break;
    }

    case CYGNUM_HAL_INTERRUPT_IMB3_MIOS_MPWM19:
    {
        cyg_uint16 mios1er1;

        HAL_READ_UINT16(CYGARC_REG_IMM_MIOS1ER1, mios1er1);
        mios1er1 |= (CYGARC_REG_IMM_MIOS1ER1_EN19);
        HAL_WRITE_UINT16(CYGARC_REG_IMM_MIOS1ER1, mios1er1);
        break;
    }

    case CYGNUM_HAL_INTERRUPT_IMB3_MIOS_MMCSM22:
    {
        cyg_uint16 mios1er1;

        HAL_READ_UINT16(CYGARC_REG_IMM_MIOS1ER1, mios1er1);
        mios1er1 |= (CYGARC_REG_IMM_MIOS1ER1_EN22);
        HAL_WRITE_UINT16(CYGARC_REG_IMM_MIOS1ER1, mios1er1);
        break;
    }

    case CYGNUM_HAL_INTERRUPT_IMB3_MIOS_MDASM27:
    {
        cyg_uint16 mios1er1;

        HAL_READ_UINT16(CYGARC_REG_IMM_MIOS1ER1, mios1er1);
        mios1er1 |= (CYGARC_REG_IMM_MIOS1ER1_EN27);
        HAL_WRITE_UINT16(CYGARC_REG_IMM_MIOS1ER1, mios1er1);
        break;
    }

    case CYGNUM_HAL_INTERRUPT_IMB3_MIOS_MDASM28:
    {
        cyg_uint16 mios1er1;

        HAL_READ_UINT16(CYGARC_REG_IMM_MIOS1ER1, mios1er1);
        mios1er1 |= (CYGARC_REG_IMM_MIOS1ER1_EN28);
        HAL_WRITE_UINT16(CYGARC_REG_IMM_MIOS1ER1, mios1er1);
        break;
    }

    case CYGNUM_HAL_INTERRUPT_IMB3_MIOS_MDASM29:
    {
        cyg_uint16 mios1er1;

        HAL_READ_UINT16(CYGARC_REG_IMM_MIOS1ER1, mios1er1);
        mios1er1 |= (CYGARC_REG_IMM_MIOS1ER1_EN29);
        HAL_WRITE_UINT16(CYGARC_REG_IMM_MIOS1ER1, mios1er1);
        break;
    }

    case CYGNUM_HAL_INTERRUPT_IMB3_MIOS_MDASM30:
    {
        cyg_uint16 mios1er1;

        HAL_READ_UINT16(CYGARC_REG_IMM_MIOS1ER1, mios1er1);
        mios1er1 |= (CYGARC_REG_IMM_MIOS1ER1_EN30);
        HAL_WRITE_UINT16(CYGARC_REG_IMM_MIOS1ER1, mios1er1);
        break;
    }

    case CYGNUM_HAL_INTERRUPT_IMB3_MIOS_MDASM31:
    {
        cyg_uint16 mios1er1;

        HAL_READ_UINT16(CYGARC_REG_IMM_MIOS1ER1, mios1er1);
        mios1er1 |= (CYGARC_REG_IMM_MIOS1ER1_EN31);
        HAL_WRITE_UINT16(CYGARC_REG_IMM_MIOS1ER1, mios1er1);
        break;
    }

    default:
        CYG_FAIL("Unknown Interrupt!!!");
        break;
    }
}

static __inline__ void
cyg_hal_interrupt_acknowledge ( cyg_uint32 vector )
{
    switch (vector) {
    case CYGNUM_HAL_INTERRUPT_SIU_IRQ0 ... CYGNUM_HAL_INTERRUPT_SIU_LVL7:
    {
        // SIU interrupt vectors
        cyg_uint32 sipend;

        // When IRQx is configured as an edge interrupt it needs to be
        // cleared. Write to INTx and IRQ/level bits are ignore so
        // it's safe to do always.
        HAL_READ_UINT32 (CYGARC_REG_IMM_SIPEND, sipend);
        sipend |= (((cyg_uint32) CYGARC_REG_IMM_SIPEND_IRQ0) 
                   >> (vector - CYGNUM_HAL_INTERRUPT_SIU_IRQ0));
        HAL_WRITE_UINT32 (CYGARC_REG_IMM_SIPEND, sipend);
        break;
    }

    case CYGNUM_HAL_INTERRUPT_SIU_TB_A:
    {
        // TimeBase A interrupt
        cyg_uint16 tbscr;

        HAL_READ_UINT16 (CYGARC_REG_IMM_TBSCR, tbscr);
        tbscr |= CYGARC_REG_IMM_TBSCR_REFA;
        tbscr &= ~(CYGARC_REG_IMM_TBSCR_REFB); // Only acknowledge the requested one
        HAL_WRITE_UINT16 (CYGARC_REG_IMM_TBSCR, tbscr);
        break;
    }

    case CYGNUM_HAL_INTERRUPT_SIU_TB_B:
    {
        // TimeBase B interrupt
        cyg_uint16 tbscr;

        HAL_READ_UINT16 (CYGARC_REG_IMM_TBSCR, tbscr);
        tbscr |= CYGARC_REG_IMM_TBSCR_REFB;
        tbscr &= ~(CYGARC_REG_IMM_TBSCR_REFA); // Only acknowledge the requested one.
        HAL_WRITE_UINT16 (CYGARC_REG_IMM_TBSCR, tbscr);
        break;
    }

    case CYGNUM_HAL_INTERRUPT_SIU_PIT:
    {
        // Periodic Interrupt
        cyg_uint16 piscr;

        HAL_READ_UINT16 (CYGARC_REG_IMM_PISCR, piscr);
        piscr |= CYGARC_REG_IMM_PISCR_PS;
        HAL_WRITE_UINT16 (CYGARC_REG_IMM_PISCR, piscr);
        break;
    }

    case CYGNUM_HAL_INTERRUPT_SIU_RTC_SEC:
    {
        // Real Time Clock Second
        cyg_uint16 rtcsc;

        HAL_READ_UINT16 (CYGARC_REG_IMM_RTCSC, rtcsc);
        rtcsc |= CYGARC_REG_IMM_RTCSC_SEC;
        rtcsc &= ~(CYGARC_REG_IMM_RTCSC_ALR); // Only acknowledge the requested one
        HAL_WRITE_UINT16 (CYGARC_REG_IMM_RTCSC, rtcsc);
        break;
    }

    case CYGNUM_HAL_INTERRUPT_SIU_RTC_ALR:
    {
        // Real Time Clock Alarm
        cyg_uint16 rtcsc;

        HAL_READ_UINT16 (CYGARC_REG_IMM_RTCSC, rtcsc);
        rtcsc |= CYGARC_REG_IMM_RTCSC_ALR;
        rtcsc &= ~(CYGARC_REG_IMM_RTCSC_SEC); // Only acknowledge the requested one
        HAL_WRITE_UINT16 (CYGARC_REG_IMM_RTCSC, rtcsc);
        break;
    }

    case CYGNUM_HAL_INTERRUPT_SIU_COL:
    {
        cyg_uint16 colir;

        HAL_READ_UINT16(CYGARC_REG_IMM_COLIR, colir);
        colir |= CYGARC_REG_IMM_COLIR_COLIS;
        HAL_WRITE_UINT16(CYGARC_REG_IMM_COLIR, colir);
        break;
    }

    case CYGNUM_HAL_INTERRUPT_IMB3_QUADCA_CI1:
    {
        cyg_uint16 quasr0;

        HAL_READ_UINT16(CYGARC_REG_IMM_QUASR0_A, quasr0);
        quasr0 &= ~(CYGARC_REG_IMM_QUASR0_CF1);
        HAL_WRITE_UINT16(CYGARC_REG_IMM_QUASR0_A, quasr0);
        break;
    }

    case CYGNUM_HAL_INTERRUPT_IMB3_QUADCA_PI1:
    { 
        cyg_uint16 quasr0;

        HAL_READ_UINT16(CYGARC_REG_IMM_QUASR0_A, quasr0);
        quasr0 &= ~(CYGARC_REG_IMM_QUASR0_PF1);
        HAL_WRITE_UINT16(CYGARC_REG_IMM_QUASR0_A, quasr0);
        break;
    }

    case CYGNUM_HAL_INTERRUPT_IMB3_QUADCA_CI2:
    {
        cyg_uint16 quasr0;

        HAL_READ_UINT16(CYGARC_REG_IMM_QUASR0_A, quasr0);
        quasr0 &= ~(CYGARC_REG_IMM_QUASR0_CF2);
        HAL_WRITE_UINT16(CYGARC_REG_IMM_QUASR0_A, quasr0);
        break;
    }

    case CYGNUM_HAL_INTERRUPT_IMB3_QUADCA_PI2:
    {
        cyg_uint16 quasr0;

        HAL_READ_UINT16(CYGARC_REG_IMM_QUASR0_A, quasr0);
        quasr0 &= ~(CYGARC_REG_IMM_QUASR0_PF2);
        HAL_WRITE_UINT16(CYGARC_REG_IMM_QUASR0_A, quasr0);
        break;
    }

    case CYGNUM_HAL_INTERRUPT_IMB3_QUADCB_CI1:
    {
        cyg_uint16 quasr0;

        HAL_READ_UINT16(CYGARC_REG_IMM_QUASR0_B, quasr0);
        quasr0 &= ~(CYGARC_REG_IMM_QUASR0_CF1);
        HAL_WRITE_UINT16(CYGARC_REG_IMM_QUASR0_B, quasr0);
        break;
    }

    case CYGNUM_HAL_INTERRUPT_IMB3_QUADCB_PI1:
    {
        cyg_uint16 quasr0;

        HAL_READ_UINT16(CYGARC_REG_IMM_QUASR0_B, quasr0);
        quasr0 &= ~(CYGARC_REG_IMM_QUASR0_PF1);
        HAL_WRITE_UINT16(CYGARC_REG_IMM_QUASR0_B, quasr0);
        break;
    }

    case CYGNUM_HAL_INTERRUPT_IMB3_QUADCB_CI2:
    {
        cyg_uint16 quasr0;

        HAL_READ_UINT16(CYGARC_REG_IMM_QUASR0_B, quasr0);
        quasr0 &= ~(CYGARC_REG_IMM_QUASR0_CF2);
        HAL_WRITE_UINT16(CYGARC_REG_IMM_QUASR0_B, quasr0);
        break;
    }

    case CYGNUM_HAL_INTERRUPT_IMB3_QUADCB_PI2:
    {
        cyg_uint16 quasr0;

        HAL_READ_UINT16(CYGARC_REG_IMM_QUASR0_B, quasr0);
        quasr0 &= ~(CYGARC_REG_IMM_QUASR0_PF2);
        HAL_WRITE_UINT16(CYGARC_REG_IMM_QUASR0_B, quasr0);
        break;
    }

    case CYGNUM_HAL_INTERRUPT_IMB3_SCI0_TX:
    case CYGNUM_HAL_INTERRUPT_IMB3_SCI0_TXC:
    case CYGNUM_HAL_INTERRUPT_IMB3_SCI0_RX:
        // Nothing needs to be done here
        break;

    case CYGNUM_HAL_INTERRUPT_IMB3_SCI0_IDLE:
    {
        cyg_uint16 scxsr;
   
        HAL_READ_UINT16(CYGARC_REG_IMM_SC1SR, scxsr);
        scxsr &= ~(CYGARC_REG_IMM_SCxSR_IDLE);
        HAL_WRITE_UINT16(CYGARC_REG_IMM_SC1SR, scxsr);
        break;
    }

    case CYGNUM_HAL_INTERRUPT_IMB3_SCI1_TX:
    case CYGNUM_HAL_INTERRUPT_IMB3_SCI1_TXC:
    case CYGNUM_HAL_INTERRUPT_IMB3_SCI1_RX:
        // nothing needs to be done here
        break;

    case CYGNUM_HAL_INTERRUPT_IMB3_SCI1_IDLE:
    {
        cyg_uint16 scxsr;
   
        HAL_READ_UINT16(CYGARC_REG_IMM_SC2SR, scxsr);
        scxsr &= ~(CYGARC_REG_IMM_SCxSR_IDLE);
        HAL_WRITE_UINT16(CYGARC_REG_IMM_SC2SR, scxsr);
        break;
    }

    case CYGNUM_HAL_INTERRUPT_IMB3_SCI1_RXQTHF:
    {
        cyg_uint16 qsci1sr;

        HAL_READ_UINT16(CYGARC_REG_IMM_QSCI1SR, qsci1sr);
        qsci1sr &= ~(CYGARC_REG_IMM_QSCI1SR_QTHF);
        HAL_WRITE_UINT16(CYGARC_REG_IMM_QSCI1SR, qsci1sr);
        break;
    }

    case CYGNUM_HAL_INTERRUPT_IMB3_SCI1_RXQBHF:
    {
        cyg_uint16 qsci1sr;

        HAL_READ_UINT16(CYGARC_REG_IMM_QSCI1SR, qsci1sr);
        qsci1sr &= ~(CYGARC_REG_IMM_QSCI1SR_QBHF);
        HAL_WRITE_UINT16(CYGARC_REG_IMM_QSCI1SR, qsci1sr);
        break;
    }

    case CYGNUM_HAL_INTERRUPT_IMB3_SCI1_TXQTHE:
    {
        cyg_uint16 qsci1sr;

        HAL_READ_UINT16(CYGARC_REG_IMM_QSCI1SR, qsci1sr);
        qsci1sr &= ~(CYGARC_REG_IMM_QSCI1SR_QTHE);
        HAL_WRITE_UINT16(CYGARC_REG_IMM_QSCI1SR, qsci1sr);
        break;
    }

    case CYGNUM_HAL_INTERRUPT_IMB3_SCI1_TXQBHE:
    {
        cyg_uint16 qsci1sr;

        HAL_READ_UINT16(CYGARC_REG_IMM_QSCI1SR, qsci1sr);
        qsci1sr &= ~(CYGARC_REG_IMM_QSCI1SR_QBHE);
        HAL_WRITE_UINT16(CYGARC_REG_IMM_QSCI1SR, qsci1sr);
        break;
    }

    case CYGNUM_HAL_INTERRUPT_IMB3_SPI_FI:
    {
        cyg_uint16 spsr;
  
        HAL_READ_UINT16(CYGARC_REG_IMM_SPSR, spsr);
        spsr &= ~(CYGARC_REG_IMM_SPSR_SPIF);
        HAL_WRITE_UINT16(CY