var_intr.h

来自「eCos操作系统源码」· C头文件 代码 · 共 1,900 行 · 第 1/5 页

    case CYGNUM_HAL_INTERRUPT_IMB3_TPUB_CH12:
    case CYGNUM_HAL_INTERRUPT_IMB3_TPUB_CH13:
    case CYGNUM_HAL_INTERRUPT_IMB3_TPUB_CH14:
    case CYGNUM_HAL_INTERRUPT_IMB3_TPUB_CH15:
    {
        cyg_uint16 cier;
     
        HAL_READ_UINT16(CYGARC_REG_IMM_CIER_B, cier);
        cier &= ~(((cyg_uint16)0x0001) << (vector - CYGNUM_HAL_INTERRUPT_IMB3_TPUB_CH0));
        HAL_WRITE_UINT16(CYGARC_REG_IMM_CIER_B, cier);
        break;
    }

    case CYGNUM_HAL_INTERRUPT_IMB3_MIOS_MPWM0:
    {
        cyg_uint16 mios1er0;

        HAL_READ_UINT16(CYGARC_REG_IMM_MIOS1ER0, mios1er0);
        mios1er0 &= ~(CYGARC_REG_IMM_MIOS1ER0_EN0);
        HAL_WRITE_UINT16(CYGARC_REG_IMM_MIOS1ER0, mios1er0);
        break;
    }

    case CYGNUM_HAL_INTERRUPT_IMB3_MIOS_MPWM1:
    {
        cyg_uint16 mios1er0;

        HAL_READ_UINT16(CYGARC_REG_IMM_MIOS1ER0, mios1er0);
        mios1er0 &= ~(CYGARC_REG_IMM_MIOS1ER0_EN1);
        HAL_WRITE_UINT16(CYGARC_REG_IMM_MIOS1ER0, mios1er0);
        break;
    }

    case CYGNUM_HAL_INTERRUPT_IMB3_MIOS_MPWM2:
    {
        cyg_uint16 mios1er0;

        HAL_READ_UINT16(CYGARC_REG_IMM_MIOS1ER0, mios1er0);
        mios1er0 &= ~(CYGARC_REG_IMM_MIOS1ER0_EN2);
        HAL_WRITE_UINT16(CYGARC_REG_IMM_MIOS1ER0, mios1er0);
        break;
    }

    case CYGNUM_HAL_INTERRUPT_IMB3_MIOS_MPWM3:
    {
        cyg_uint16 mios1er0;

        HAL_READ_UINT16(CYGARC_REG_IMM_MIOS1ER0, mios1er0);
        mios1er0 &= ~(CYGARC_REG_IMM_MIOS1ER0_EN3);
        HAL_WRITE_UINT16(CYGARC_REG_IMM_MIOS1ER0, mios1er0);
        break;
    }

    case CYGNUM_HAL_INTERRUPT_IMB3_MIOS_MMCSM6:
    {
        cyg_uint16 mios1er0;

        HAL_READ_UINT16(CYGARC_REG_IMM_MIOS1ER0, mios1er0);
        mios1er0 &= ~(CYGARC_REG_IMM_MIOS1ER0_EN6);
        HAL_WRITE_UINT16(CYGARC_REG_IMM_MIOS1ER0, mios1er0);
        break;
    }

    case CYGNUM_HAL_INTERRUPT_IMB3_MIOS_MDASM11:
    {
        cyg_uint16 mios1er0;

        HAL_READ_UINT16(CYGARC_REG_IMM_MIOS1ER0, mios1er0);
        mios1er0 &= ~(CYGARC_REG_IMM_MIOS1ER0_EN11);
        HAL_WRITE_UINT16(CYGARC_REG_IMM_MIOS1ER0, mios1er0);
        break;
    }

    case CYGNUM_HAL_INTERRUPT_IMB3_MIOS_MDASM12:
    {
        cyg_uint16 mios1er0;

        HAL_READ_UINT16(CYGARC_REG_IMM_MIOS1ER0, mios1er0);
        mios1er0 &= ~(CYGARC_REG_IMM_MIOS1ER0_EN12);
        HAL_WRITE_UINT16(CYGARC_REG_IMM_MIOS1ER0, mios1er0);
        break;
    }

    case CYGNUM_HAL_INTERRUPT_IMB3_MIOS_MDASM13:
    {
        cyg_uint16 mios1er0;

        HAL_READ_UINT16(CYGARC_REG_IMM_MIOS1ER0, mios1er0);
        mios1er0 &= ~(CYGARC_REG_IMM_MIOS1ER0_EN13);
        HAL_WRITE_UINT16(CYGARC_REG_IMM_MIOS1ER0, mios1er0);
        break;
    }

    case CYGNUM_HAL_INTERRUPT_IMB3_MIOS_MDASM14:
    {
        cyg_uint16 mios1er0;

        HAL_READ_UINT16(CYGARC_REG_IMM_MIOS1ER0, mios1er0);
        mios1er0 &= ~(CYGARC_REG_IMM_MIOS1ER0_EN14);
        HAL_WRITE_UINT16(CYGARC_REG_IMM_MIOS1ER0, mios1er0);
        break;
    }

    case CYGNUM_HAL_INTERRUPT_IMB3_MIOS_MDASM15:
    {
        cyg_uint16 mios1er0;

        HAL_READ_UINT16(CYGARC_REG_IMM_MIOS1ER0, mios1er0);
        mios1er0 &= ~(CYGARC_REG_IMM_MIOS1ER0_EN15);
        HAL_WRITE_UINT16(CYGARC_REG_IMM_MIOS1ER0, mios1er0);
        break;
    }

    case CYGNUM_HAL_INTERRUPT_IMB3_MIOS_MPWM16:
    {
        cyg_uint16 mios1er1;

        HAL_READ_UINT16(CYGARC_REG_IMM_MIOS1ER1, mios1er1);
        mios1er1 &= ~(CYGARC_REG_IMM_MIOS1ER1_EN16);
        HAL_WRITE_UINT16(CYGARC_REG_IMM_MIOS1ER1, mios1er1);
        break;
    }

    case CYGNUM_HAL_INTERRUPT_IMB3_MIOS_MPWM17:
    {
        cyg_uint16 mios1er1;

        HAL_READ_UINT16(CYGARC_REG_IMM_MIOS1ER1, mios1er1);
        mios1er1 &= ~(CYGARC_REG_IMM_MIOS1ER1_EN17);
        HAL_WRITE_UINT16(CYGARC_REG_IMM_MIOS1ER1, mios1er1);
        break;
    }

    case CYGNUM_HAL_INTERRUPT_IMB3_MIOS_MPWM18:
    {
        cyg_uint16 mios1er1;

        HAL_READ_UINT16(CYGARC_REG_IMM_MIOS1ER1, mios1er1);
        mios1er1 &= ~(CYGARC_REG_IMM_MIOS1ER1_EN18);
        HAL_WRITE_UINT16(CYGARC_REG_IMM_MIOS1ER1, mios1er1);
        break;
    }

    case CYGNUM_HAL_INTERRUPT_IMB3_MIOS_MPWM19:
    {
        cyg_uint16 mios1er1;

        HAL_READ_UINT16(CYGARC_REG_IMM_MIOS1ER1, mios1er1);
        mios1er1 &= ~(CYGARC_REG_IMM_MIOS1ER1_EN19);
        HAL_WRITE_UINT16(CYGARC_REG_IMM_MIOS1ER1, mios1er1);
        break;
    }

    case CYGNUM_HAL_INTERRUPT_IMB3_MIOS_MMCSM22:
    {
        cyg_uint16 mios1er1;

        HAL_READ_UINT16(CYGARC_REG_IMM_MIOS1ER1, mios1er1);
        mios1er1 &= ~(CYGARC_REG_IMM_MIOS1ER1_EN22);
        HAL_WRITE_UINT16(CYGARC_REG_IMM_MIOS1ER1, mios1er1);
        break;
    }

    case CYGNUM_HAL_INTERRUPT_IMB3_MIOS_MDASM27:
    {
        cyg_uint16 mios1er1;

        HAL_READ_UINT16(CYGARC_REG_IMM_MIOS1ER1, mios1er1);
        mios1er1 &= ~(CYGARC_REG_IMM_MIOS1ER1_EN27);
        HAL_WRITE_UINT16(CYGARC_REG_IMM_MIOS1ER1, mios1er1);
        break;
    }

    case CYGNUM_HAL_INTERRUPT_IMB3_MIOS_MDASM28:
    {
        cyg_uint16 mios1er1;

        HAL_READ_UINT16(CYGARC_REG_IMM_MIOS1ER1, mios1er1);
        mios1er1 &= ~(CYGARC_REG_IMM_MIOS1ER1_EN28);
        HAL_WRITE_UINT16(CYGARC_REG_IMM_MIOS1ER1, mios1er1);
        break;
    }

    case CYGNUM_HAL_INTERRUPT_IMB3_MIOS_MDASM29:
    {
        cyg_uint16 mios1er1;

        HAL_READ_UINT16(CYGARC_REG_IMM_MIOS1ER1, mios1er1);
        mios1er1 &= ~(CYGARC_REG_IMM_MIOS1ER1_EN29);
        HAL_WRITE_UINT16(CYGARC_REG_IMM_MIOS1ER1, mios1er1);
        break;
    }

    case CYGNUM_HAL_INTERRUPT_IMB3_MIOS_MDASM30:
    {
        cyg_uint16 mios1er1;

        HAL_READ_UINT16(CYGARC_REG_IMM_MIOS1ER1, mios1er1);
        mios1er1 &= ~(CYGARC_REG_IMM_MIOS1ER1_EN30);
        HAL_WRITE_UINT16(CYGARC_REG_IMM_MIOS1ER1, mios1er1);
        break;
    }

    case CYGNUM_HAL_INTERRUPT_IMB3_MIOS_MDASM31:
    {
        cyg_uint16 mios1er1;

        HAL_READ_UINT16(CYGARC_REG_IMM_MIOS1ER1, mios1er1);
        mios1er1 &= ~(CYGARC_REG_IMM_MIOS1ER1_EN31);
        HAL_WRITE_UINT16(CYGARC_REG_IMM_MIOS1ER1, mios1er1);
        break;
    }

    default:
        CYG_FAIL("Unknown Interrupt!!!");
        break;
    }
}

static __inline__ void
cyg_hal_interrupt_unmask ( cyg_uint32 vector )
{
    switch (vector) {
    case CYGNUM_HAL_INTERRUPT_SIU_IRQ0 ... CYGNUM_HAL_INTERRUPT_SIU_LVL7:
    {
        // SIU interrupt vectors
        cyg_uint32 simask;

        HAL_READ_UINT32 (CYGARC_REG_IMM_SIMASK, simask);
        simask |= (((cyg_uint32) CYGARC_REG_IMM_SIMASK_IRM0) 
                    >> (vector - CYGNUM_HAL_INTERRUPT_SIU_IRQ0));
        HAL_WRITE_UINT32 (CYGARC_REG_IMM_SIMASK, simask);
        break;
    }
    case CYGNUM_HAL_INTERRUPT_SIU_TB_A :
    {
        // TimeBase A interrupt
        cyg_uint16 tbscr;

        HAL_READ_UINT16 (CYGARC_REG_IMM_TBSCR, tbscr);
        tbscr |= (CYGARC_REG_IMM_TBSCR_REFAE);
        tbscr &= ~(CYGARC_REG_IMM_TBSCR_REFA); // Prevent from clearing interrupt flags
        tbscr &= ~(CYGARC_REG_IMM_TBSCR_REFB); // accidently. Just do what is asked.
        HAL_WRITE_UINT16 (CYGARC_REG_IMM_TBSCR, tbscr);
        break;
    }
    case CYGNUM_HAL_INTERRUPT_SIU_TB_B :
    {
        // TimeBase B interrupt
        cyg_uint16 tbscr;

        HAL_READ_UINT16 (CYGARC_REG_IMM_TBSCR, tbscr);
        tbscr |= (CYGARC_REG_IMM_TBSCR_REFBE);
        tbscr &= ~(CYGARC_REG_IMM_TBSCR_REFA); // Prevent from clearing interrupt flags
        tbscr &= ~(CYGARC_REG_IMM_TBSCR_REFB); // accidently. Just do what is asked.
        HAL_WRITE_UINT16 (CYGARC_REG_IMM_TBSCR, tbscr);
        break;
    }
    case CYGNUM_HAL_INTERRUPT_SIU_PIT:
    {
        // Periodic Interrupt
        cyg_uint16 piscr;

        HAL_READ_UINT16 (CYGARC_REG_IMM_PISCR, piscr);
        piscr |= (CYGARC_REG_IMM_PISCR_PIE);
        piscr &= ~(CYGARC_REG_IMM_PISCR_PS); // Prevent from clearing interrupt flag.
        HAL_WRITE_UINT16 (CYGARC_REG_IMM_PISCR, piscr);
        break;
    }
    case CYGNUM_HAL_INTERRUPT_SIU_RTC_SEC:
    {
        // Real Time Clock Second
        cyg_uint16 rtcsc;

        HAL_READ_UINT16 (CYGARC_REG_IMM_RTCSC, rtcsc);
        rtcsc |= (CYGARC_REG_IMM_RTCSC_SIE);
        rtcsc &= ~(CYGARC_REG_IMM_RTCSC_SEC); // Prevent from clearing interrupt flags
        rtcsc &= ~(CYGARC_REG_IMM_RTCSC_ALR); // accidently. Just do what is asdked.
        HAL_WRITE_UINT16 (CYGARC_REG_IMM_RTCSC, rtcsc);
        break;
    }
    case CYGNUM_HAL_INTERRUPT_SIU_RTC_ALR:
    {
        // Real Time Clock Alarm
        cyg_uint16 rtcsc;

        HAL_READ_UINT16 (CYGARC_REG_IMM_RTCSC, rtcsc);
        rtcsc |= (CYGARC_REG_IMM_RTCSC_ALE);
        rtcsc &= ~(CYGARC_REG_IMM_RTCSC_SEC); // Prevent from clearing interrupt flags
        rtcsc &= ~(CYGARC_REG_IMM_RTCSC_ALR); // accidently. Just do what is asdked.
        HAL_WRITE_UINT16 (CYGARC_REG_IMM_RTCSC, rtcsc);
        break;
    }

    case CYGNUM_HAL_INTERRUPT_SIU_COL:
    {
        // PLL change of lock
        cyg_uint16 colir;

        HAL_READ_UINT16 (CYGARC_REG_IMM_COLIR, colir);
        colir |= (CYGARC_REG_IMM_COLIR_COLIE);
        colir &= ~(CYGARC_REG_IMM_COLIR_COLIS); // Prevent from clearing interrupt flag accidently.
        HAL_WRITE_UINT16 (CYGARC_REG_IMM_COLIR, colir);
        break;
    }

    case CYGNUM_HAL_INTERRUPT_IMB3_QUADCA_CI1:
    {
        cyg_uint16 quacr1;

        HAL_READ_UINT16(CYGARC_REG_IMM_QUACR1_A, quacr1);
        quacr1 |= (CYGARC_REG_IMM_QUACR1_CIE1);
        HAL_WRITE_UINT16(CYGARC_REG_IMM_QUACR1_A, quacr1);
        break;
    }

    case CYGNUM_HAL_INTERRUPT_IMB3_QUADCA_PI1:
    {
        cyg_uint16 quacr1;

        HAL_READ_UINT16(CYGARC_REG_IMM_QUACR1_A, quacr1);
        quacr1 |= (CYGARC_REG_IMM_QUACR1_PIE1);
        HAL_WRITE_UINT16(CYGARC_REG_IMM_QUACR1_A, quacr1);
        break;
    }

    case CYGNUM_HAL_INTERRUPT_IMB3_QUADCA_CI2:
    {
        cyg_uint16 quacr2;

        HAL_READ_UINT16(CYGARC_REG_IMM_QUACR2_A, quacr2);
        quacr2 |= (CYGARC_REG_IMM_QUACR2_CIE2);
        HAL_WRITE_UINT16(CYGARC_REG_IMM_QUACR2_A, quacr2);
        break;
    }

    case CYGNUM_HAL_INTERRUPT_IMB3_QUADCA_PI2:
    {
        cyg_uint16 quacr2;

        HAL_READ_UINT16(CYGARC_REG_IMM_QUACR2_A, quacr2);
        quacr2 |= (CYGARC_REG_IMM_QUACR2_PIE2);
        HAL_WRITE_UINT16(CYGARC_REG_IMM_QUACR2_A, quacr2);
        break;
    }

    case CYGNUM_HAL_INTERRUPT_IMB3_QUADCB_CI1:
    {
        cyg_uint16 quacr1;

        HAL_READ_UINT16(CYGARC_REG_IMM_QUACR1_B, quacr1);
        quacr1 |= (CYGARC_REG_IMM_QUACR1_CIE1);
        HAL_WRITE_UINT16(CYGARC_REG_IMM_QUACR1_B, quacr1);
        break;
    }

    case CYGNUM_HAL_INTERRUPT_IMB3_QUADCB_PI1:
    {
        cyg_uint16 quacr1;

        HAL_READ_UINT16(CYGARC_REG_IMM_QUACR1_B, quacr1);
        quacr1 |= (CYGARC_REG_IMM_QUACR1_PIE1);
        HAL_WRITE_UINT16(CYGARC_REG_IMM_QUACR1_B, quacr1);
        break;
    }

    case CYGNUM_HAL_INTERRUPT_IMB3_QUADCB_CI2:
    {
        cyg_uint16 quacr2;

        HAL_READ_UINT16(CYGARC_REG_IMM_QUACR2_B, quacr2);
        quacr2 |= (CYGARC_REG_IMM_QUACR2_CIE2);
        HAL_WRITE_UINT16(CYGARC_REG_IMM_QUACR2_B, quacr2);
        break;
    }

    case CYGNUM_HAL_INTERRUPT_IMB3_QUADCB_PI2:
    {
        cyg_uint16 quacr2;