📄 var_regs.h
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//-------------------------------------#define CYGARC_REG_IMM_QSMCMMCR (CYGARC_REG_IMM_BASE+0x9000)#define CYGARC_REG_IMM_QTEST (CYGARC_REG_IMM_BASE+0x9002)#define CYGARC_REG_IMM_QDSCI_IL (CYGARC_REG_IMM_BASE+0x9004)#define CYGARC_REG_IMM_QSPI_IL (CYGARC_REG_IMM_BASE+0x9006)#define CYGARC_REG_IMM_SCC1R0 (CYGARC_REG_IMM_BASE+0x9008)#define CYGARC_REG_IMM_SCC1R1 (CYGARC_REG_IMM_BASE+0x900a)#define CYGARC_REG_IMM_SC1SR (CYGARC_REG_IMM_BASE+0x900c)#define CYGARC_REG_IMM_SC1DR (CYGARC_REG_IMM_BASE+0x900e)#define CYGARC_REG_IMM_PORTQS (CYGARC_REG_IMM_BASE+0x9014)#define CYGARC_REG_IMM_PQSPAR_DDRQST (CYGARC_REG_IMM_BASE+0x9016)#define CYGARC_REG_IMM_SPCR0 (CYGARC_REG_IMM_BASE+0x9018)#define CYGARC_REG_IMM_SPCR1 (CYGARC_REG_IMM_BASE+0x901a)#define CYGARC_REG_IMM_SPCR2 (CYGARC_REG_IMM_BASE+0x901c)#define CYGARC_REG_IMM_SPCR3 (CYGARC_REG_IMM_BASE+0x901e)#define CYGARC_REG_IMM_SPSR (CYGARC_REG_IMM_BASE+0x901f)#define CYGARC_REG_IMM_SCC2R0 (CYGARC_REG_IMM_BASE+0x9020)#define CYGARC_REG_IMM_SCC2R1 (CYGARC_REG_IMM_BASE+0x9022)#define CYGARC_REG_IMM_SC2SR (CYGARC_REG_IMM_BASE+0x9024)#define CYGARC_REG_IMM_SC2DR (CYGARC_REG_IMM_BASE+0x9026)#define CYGARC_REG_IMM_QSCI1CR (CYGARC_REG_IMM_BASE+0x9028)#define CYGARC_REG_IMM_QSCI1SR (CYGARC_REG_IMM_BASE+0x902a)#define CYGARC_REG_IMM_SCTQ (CYGARC_REG_IMM_BASE+0x902c)#define CYGARC_REG_IMM_SCRQ (CYGARC_REG_IMM_BASE+0x904c)#define CYGARC_REG_IMM_RECRAM (CYGARC_REG_IMM_BASE+0x9140)#define CYGARC_REG_IMM_TRAN_RAM (CYGARC_REG_IMM_BASE+0x9180)#define CYGARC_REG_IMM_COMD_RAM (CYGARC_REG_IMM_BASE+0x91c0) //------------------------------------- // MIOS1 (Modular Input/Output Subsystem) //------------------------------------- // MPIOS Pulse width modulation submodule 0#define CYGARC_REG_IMM_MPWMSMPERR_0 (CYGARC_REG_IMM_BASE+0xa000)#define CYGARC_REG_IMM_MPWMSMPULR_0 (CYGARC_REG_IMM_BASE+0xa002)#define CYGARC_REG_IMM_MPWMSMCNTR_0 (CYGARC_REG_IMM_BASE+0xa004)#define CYGARC_REG_IMM_MPWMSMSCR_0 (CYGARC_REG_IMM_BASE+0xa006) // MPIOS Pulse width modulation submodule 1#define CYGARC_REG_IMM_MPWMSMPERR_1 (CYGARC_REG_IMM_BASE+0xa008)#define CYGARC_REG_IMM_MPWMSMPULR_1 (CYGARC_REG_IMM_BASE+0xa00a)#define CYGARC_REG_IMM_MPWMSMCNTR_1 (CYGARC_REG_IMM_BASE+0xa00c)#define CYGARC_REG_IMM_MPWMSMSCR_1 (CYGARC_REG_IMM_BASE+0xa00e) // MPIOS Pulse width modulation submodule 2#define CYGARC_REG_IMM_MPWMSMPERR_2 (CYGARC_REG_IMM_BASE+0xa010)#define CYGARC_REG_IMM_MPWMSMPULR_2 (CYGARC_REG_IMM_BASE+0xa012)#define CYGARC_REG_IMM_MPWMSMCNTR_2 (CYGARC_REG_IMM_BASE+0xa014)#define CYGARC_REG_IMM_MPWMSMSCR_2 (CYGARC_REG_IMM_BASE+0xa016) // MPIOS Pulse width modulation submodule 3#define CYGARC_REG_IMM_MPWMSMPERR_3 (CYGARC_REG_IMM_BASE+0xa018)#define CYGARC_REG_IMM_MPWMSMPULR_3 (CYGARC_REG_IMM_BASE+0xa01a)#define CYGARC_REG_IMM_MPWMSMCNTR_3 (CYGARC_REG_IMM_BASE+0xa01c)#define CYGARC_REG_IMM_MPWMSMSCR_3 (CYGARC_REG_IMM_BASE+0xa01e) // MIOS Modulus counter submodule 6#define CYGARC_REG_IMM_MMCSMCNT_6 (CYGARC_REG_IMM_BASE+0xa030)#define CYGARC_REG_IMM_MMCSMML_6 (CYGARC_REG_IMM_BASE+0xa032)#define CYGARC_REG_IMM_MMCSMSCRD_6 (CYGARC_REG_IMM_BASE+0xa034)#define CYGARC_REG_IMM_MMCSMSCR_6 (CYGARC_REG_IMM_BASE+0xa036) // MIOS Double Action submodule 11#define CYGARC_REG_IMM_MDASMAR_11 (CYGARC_REG_IMM_BASE+0xa058)#define CYGARC_REG_IMM_MDASMBR_11 (CYGARC_REG_IMM_BASE+0xa05a)#define CYGARC_REG_IMM_MDASMSCRD_11 (CYGARC_REG_IMM_BASE+0xa05c)#define CYGARC_REG_IMM_MDASMSCR_11 (CYGARC_REG_IMM_BASE+0xa05e) // MIOS Double Action submodule 12#define CYGARC_REG_IMM_MDASMAR_12 (CYGARC_REG_IMM_BASE+0xa060)#define CYGARC_REG_IMM_MDASMBR_12 (CYGARC_REG_IMM_BASE+0xa062)#define CYGARC_REG_IMM_MDASMSCRD_12 (CYGARC_REG_IMM_BASE+0xa064)#define CYGARC_REG_IMM_MDASMSCR_12 (CYGARC_REG_IMM_BASE+0xa066) // MIOS Double Action submodule 13#define CYGARC_REG_IMM_MDASMAR_13 (CYGARC_REG_IMM_BASE+0xa068)#define CYGARC_REG_IMM_MDASMBR_13 (CYGARC_REG_IMM_BASE+0xa06a)#define CYGARC_REG_IMM_MDASMSCRD_13 (CYGARC_REG_IMM_BASE+0xa06c)#define CYGARC_REG_IMM_MDASMSCR_13 (CYGARC_REG_IMM_BASE+0xa06e) // MIOS Double Action submodule 14#define CYGARC_REG_IMM_MDASMAR_14 (CYGARC_REG_IMM_BASE+0xa070)#define CYGARC_REG_IMM_MDASMBR_14 (CYGARC_REG_IMM_BASE+0xa072)#define CYGARC_REG_IMM_MDASMSCRD_14 (CYGARC_REG_IMM_BASE+0xa074)#define CYGARC_REG_IMM_MDASMSCR_14 (CYGARC_REG_IMM_BASE+0xa076) // MIOS Double Action submodule 15#define CYGARC_REG_IMM_MDASMAR_15 (CYGARC_REG_IMM_BASE+0xa078)#define CYGARC_REG_IMM_MDASMBR_15 (CYGARC_REG_IMM_BASE+0xa07a)#define CYGARC_REG_IMM_MDASMSCRD_15 (CYGARC_REG_IMM_BASE+0xa07c)#define CYGARC_REG_IMM_MDASMSCR_15 (CYGARC_REG_IMM_BASE+0xa07e) // MPIOS Pulse width modulation submodule 16#define CYGARC_REG_IMM_MPWMSMPERR_16 (CYGARC_REG_IMM_BASE+0xa080)#define CYGARC_REG_IMM_MPWMSMPULR_16 (CYGARC_REG_IMM_BASE+0xa082)#define CYGARC_REG_IMM_MPWMSMCNTR_16 (CYGARC_REG_IMM_BASE+0xa084)#define CYGARC_REG_IMM_MPWMSMSCR_16 (CYGARC_REG_IMM_BASE+0xa086) // MPIOS Pulse width modulation submodule 17#define CYGARC_REG_IMM_MPWMSMPERR_17 (CYGARC_REG_IMM_BASE+0xa088)#define CYGARC_REG_IMM_MPWMSMPULR_17 (CYGARC_REG_IMM_BASE+0xa08a)#define CYGARC_REG_IMM_MPWMSMCNTR_17 (CYGARC_REG_IMM_BASE+0xa08c)#define CYGARC_REG_IMM_MPWMSMSCR_17 (CYGARC_REG_IMM_BASE+0xa08e) // MPIOS Pulse width modulation submodule 18#define CYGARC_REG_IMM_MPWMSMPERR_18 (CYGARC_REG_IMM_BASE+0xa090)#define CYGARC_REG_IMM_MPWMSMPULR_18 (CYGARC_REG_IMM_BASE+0xa092)#define CYGARC_REG_IMM_MPWMSMCNTR_18 (CYGARC_REG_IMM_BASE+0xa094)#define CYGARC_REG_IMM_MPWMSMSCR_18 (CYGARC_REG_IMM_BASE+0xa096) // MPIOS Pulse width modulation submodule 19#define CYGARC_REG_IMM_MPWMSMPERR_19 (CYGARC_REG_IMM_BASE+0xa098)#define CYGARC_REG_IMM_MPWMSMPULR_19 (CYGARC_REG_IMM_BASE+0xa09a)#define CYGARC_REG_IMM_MPWMSMCNTR_19 (CYGARC_REG_IMM_BASE+0xa09c)#define CYGARC_REG_IMM_MPWMSMSCR_19 (CYGARC_REG_IMM_BASE+0xa09e) // MIOS Modulus counter submodule 22#define CYGARC_REG_IMM_MMCSMCNT_22 (CYGARC_REG_IMM_BASE+0xa0b0)#define CYGARC_REG_IMM_MMCSMML_22 (CYGARC_REG_IMM_BASE+0xa0b2)#define CYGARC_REG_IMM_MMCSMSCRD_22 (CYGARC_REG_IMM_BASE+0xa0b4)#define CYGARC_REG_IMM_MMCSMSCR_22 (CYGARC_REG_IMM_BASE+0xa0b6) // MIOS Double action submodule 27#define CYGARC_REG_IMM_MDASMAR_27 (CYGARC_REG_IMM_BASE+0xa0d8)#define CYGARC_REG_IMM_MDASMBR_27 (CYGARC_REG_IMM_BASE+0xa0da)#define CYGARC_REG_IMM_MDASMSCRD_27 (CYGARC_REG_IMM_BASE+0xa0dc)#define CYGARC_REG_IMM_MDASMSCR_27 (CYGARC_REG_IMM_BASE+0xa0de) // MIOS Double action submodule 28#define CYGARC_REG_IMM_MDASMAR_28 (CYGARC_REG_IMM_BASE+0xa0e0)#define CYGARC_REG_IMM_MDASMBR_28 (CYGARC_REG_IMM_BASE+0xa0e2)#define CYGARC_REG_IMM_MDASMSCRD_28 (CYGARC_REG_IMM_BASE+0xa0e4)#define CYGARC_REG_IMM_MDASMSCR_28 (CYGARC_REG_IMM_BASE+0xa0e6) // MIOS Double action submodule 29#define CYGARC_REG_IMM_MDASMAR_29 (CYGARC_REG_IMM_BASE+0xa0e8)#define CYGARC_REG_IMM_MDASMBR_29 (CYGARC_REG_IMM_BASE+0xa0ea)#define CYGARC_REG_IMM_MDASMSCRD_29 (CYGARC_REG_IMM_BASE+0xa0ec)#define CYGARC_REG_IMM_MDASMSCR_29 (CYGARC_REG_IMM_BASE+0xa0ee) // MIOS Double action submodule 30#define CYGARC_REG_IMM_MDASMAR_30 (CYGARC_REG_IMM_BASE+0xa0f0)#define CYGARC_REG_IMM_MDASMBR_30 (CYGARC_REG_IMM_BASE+0xa0f2)#define CYGARC_REG_IMM_MDASMSCRD_30 (CYGARC_REG_IMM_BASE+0xa0f4)#define CYGARC_REG_IMM_MDASMSCR_30 (CYGARC_REG_IMM_BASE+0xa0f6) // MIOS Double action submodule 31#define CYGARC_REG_IMM_MDASMAR_31 (CYGARC_REG_IMM_BASE+0x0af8)#define CYGARC_REG_IMM_MDASMBR_31 (CYGARC_REG_IMM_BASE+0xa0fa)#define CYGARC_REG_IMM_MDASMSCRD_31 (CYGARC_REG_IMM_BASE+0xa0fc)#define CYGARC_REG_IMM_MDASMSCR_31 (CYGARC_REG_IMM_BASE+0xa0fe) // MIOS Paralell port I/O submodule#define CYGARC_REG_IMM_MPIOSMDR (CYGARC_REG_IMM_BASE+0xa100)#define CYGARC_REG_IMM_MPIOSMDDR (CYGARC_REG_IMM_BASE+0xa102) // MIOS Bus interface Submodule#define CYGARC_REG_IMM_MIOS1TPCR (CYGARC_REG_IMM_BASE+0xa800)#define CYGARC_REG_IMM_MIOS1VNR (CYGARC_REG_IMM_BASE+0xa802)#define CYGARC_REG_IMM_MIOS1MCR (CYGARC_REG_IMM_BASE+0xa806) // MIOS Counter / Prescaler submodule#define CYGARC_REG_IMM_MCPSMSCR (CYGARC_REG_IMM_BASE+0xa816) // MIOS Interrupt request submodule 0#define CYGARC_REG_IMM_MIOS1SR0 (CYGARC_REG_IMM_BASE+0xac00)#define CYGARC_REG_IMM_MIOS1ER0 (CYGARC_REG_IMM_BASE+0xac04)#define CYGARC_REG_IMM_MIOS1RPR0 (CYGARC_REG_IMM_BASE+0xac06)#define CYGARC_REG_IMM_MIOS1LVL0 (CYGARC_REG_IMM_BASE+0xac30) // Mios Interrupt request submodule 1#define CYGARC_REG_IMM_MIOS1SR1 (CYGARC_REG_IMM_BASE+0xac40)#define CYGARC_REG_IMM_MIOS1ER1 (CYGARC_REG_IMM_BASE+0xac44)#define CYGARC_REG_IMM_MIOS1RPR1 (CYGARC_REG_IMM_BASE+0xac46)#define CYGARC_REG_IMM_MIOS1LVL1 (CYGARC_REG_IMM_BASE+0xac70) //------------------------------------- // TouCAN (CAN 2.0B Controller) //------------------------------------- // TouCAN_A#define CYGARC_REG_IMM_TCNMCR_A (CYGARC_REG_IMM_BASE+0xb080)#define CYGARC_REG_IMM_TTR_A (CYGARC_REG_IMM_BASE+0xb082)#define CYGARC_REG_IMM_CANICR_A (CYGARC_REG_IMM_BASE+0xb084)#define CYGARC_REG_IMM_CANCTRL0_A_CANCTRL1_A (CYGARC_REG_IMM_BASE+0xb086)#define CYGARC_REG_IMM_PRESDIV_A_CTRL2_A (CYGARC_REG_IMM_BASE+0xb088)#define CYGARC_REG_IMM_TIMER_A (CYGARC_REG_IMM_BASE+0xb08a)#define CYGARC_REG_IMM_RXGMASKHI_A (CYGARC_REG_IMM_BASE+0xb090)#define CYGARC_REG_IMM_RXGMASKLO_A (CYGARC_REG_IMM_BASE+0xb092)#define CYGARC_REG_IMM_RX14MASKHI_A (CYGARC_REG_IMM_BASE+0xb094)#define CYGARC_REG_IMM_RX14MASKLO_A (CYGARC_REG_IMM_BASE+0xb096)#define CYGARC_REG_IMM_RX15MASKHI_A (CYGARC_REG_IMM_BASE+0xb098)#define CYGARC_REG_IMM_RX15MASKLO_A (CYGARC_REG_IMM_BASE+0xb09a)#define CYGARC_REG_IMM_ESTAT_A (CYGARC_REG_IMM_BASE+0xb0a0)#define CYGARC_REG_IMM_IMASK_A (CYGARC_REG_IMM_BASE+0xb0a2)#define CYGARC_REG_IMM_IFLAG_A (CYGARC_REG_IMM_BASE+0xb0a4)#define CYGARC_REG_IMM_RXECTR_A_TXECTR_A (CYGARC_REG_IMM_BASE+0xb0a6) // TouCAN_B#define CYGARC_REG_IMM_TCNMCR_B (CYGARC_REG_IMM_BASE+0xb480)#define CYGARC_REG_IMM_TTR_B (CYGARC_REG_IMM_BASE+0xb482)#define CYGARC_REG_IMM_CANICR_B (CYGARC_REG_IMM_BASE+0xb484)#define CYGARC_REG_IMM_CANCTRL0_B_CANCTRL1_B (CYGARC_REG_IMM_BASE+0xb486)#define CYGARC_REG_IMM_PRESDIV_B_CTRL2_B (CYGARC_REG_IMM_BASE+0xb488)#define CYGARC_REG_IMM_TIMER_B (CYGARC_REG_IMM_BASE+0xb48a)#define CYGARC_REG_IMM_RXGMASKHI_B (CYGARC_REG_IMM_BASE+0xb490)#define CYGARC_REG_IMM_RXGMASKLO_B (CYGARC_REG_IMM_BASE+0xb492)#define CYGARC_REG_IMM_RX14MASKHI_B (CYGARC_REG_IMM_BASE+0xb494)#define CYGARC_REG_IMM_RX14MASKLO_B (CYGARC_REG_IMM_BASE+0xb496)#define CYGARC_REG_IMM_RX15MASKHI_B (CYGARC_REG_IMM_BASE+0xb498)#define CYGARC_REG_IMM_RX15MASKLO_B (CYGARC_REG_IMM_BASE+0xb49a)#define CYGARC_REG_IMM_ESTAT_B (CYGARC_REG_IMM_BASE+0xb4a0)#define CYGARC_REG_IMM_IMASK_B (CYGARC_REG_IMM_BASE+0xb4a2)#define CYGARC_REG_IMM_IFLAG_B (CYGARC_REG_IMM_BASE+0xb4a4)#define CYGARC_REG_IMM_RXECTR_A_TXECTR_B (CYGARC_REG_IMM_BASE+0xb4a6) //------------------------------------- // UIMB (U-Bus to IMB3 Bus Interface) //-------------------------------------#define CYGARC_REG_IMM_UMCR (CYGARC_REG_IMM_BASE+0xbf80)#define CYGARC_REG_IMM_UTSTCREG (CYGARC_REG_IMM_BASE+0xbf90)#define CYGARC_REG_IMM_UIPEND (CYGARC_REG_IMM_BASE+0xbfa0) //------------------------------------- // SRAM (Static RAM Access memory) //-------------------------------------#define CYGARC_REG_IMM_SRAMMCR_A (CYGARC_REG_IMM_BASE+0x84000)#define CYGARC_REG_IMM_SRAMTST_A (CYGARC_REG_IMM_BASE+0x84004)#define CYGARC_REG_IMM_SRAMMCR_B (CYGARC_REG_IMM_BASE+0x84008)#define CYGARC_REG_IMM_SRAMTST_B (CYGARC_REG_IMM_BASE+0x8400c)#ifdef CYGARC_HAL_COMMON_EXPORT_CPU_MACROS// definitions without CYGARC_REG_ can come here. If there is a need for it ....#endif//-----------------------------------------------------------------------------#endif // ifdef CYGONCE_HAL_VAR_REGS_H// End of var_regs.h⌨️ 快捷键说明
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