var_regs.h

eCos操作系统源码

#define CYGARC_REG_IMM_SIEL_ED4        0x00800000  // Falling edge external interrupt prioriry 4
#define CYGARC_REG_IMM_SIEL_WM4        0x00400000  // Wake-up mask external interrupt priority 4
#define CYGARC_REG_IMM_SIEL_ED5        0x00200000  // Falling edge external interrupt priority 5
#define CYGARC_REG_IMM_SIEL_WM5        0x00100000  // Wake-up mask external interrupt priority 5
#define CYGARC_REG_IMM_SIEL_ED6        0x00080000  // Falling edge external interrupt priority 6
#define CYGARC_REG_IMM_SIEL_WM6        0x00040000  // Wake-up mask external interrupt priority 6
#define CYGARC_REG_IMM_SIEL_ED7        0x00020000  // Falling edge external interrupt priority 7
#define CYGARC_REG_IMM_SIEL_WM7        0x00010000  // Wake-up mask external interrupt priority 7

//-----------------------------------------------------------------------------
// Memory controller
#define CYGARC_REG_IMM_BR_BA_MASK      0xffff8000       // base address
#define CYGARC_REG_IMM_BR_AT_MASK      0x00007000       // address type
#define CYGARC_REG_IMM_BR_PS_8         0x00000400       // port size 8 bits
#define CYGARC_REG_IMM_BR_PS_16        0x00000800       // port size 16 bits
#define CYGARC_REG_IMM_BR_PS_32        0x00000000       // port size 32 bits
#define CYGARC_REG_IMM_BR_WP           0x00000100       // write protect
#define CYGARC_REG_IMM_BR_WEBS         0x00000020       // write enable byte select
#define CYGARC_REG_IMM_BR_TBDIP        0x00000010       // toggle burst data in progress
#define CYGARC_REG_IMM_BR_LBDIP        0x00000008       // late burst data in progress
#define CYGARC_REG_IMM_BR_SETA         0x00000004       // externam transfer acknowledge
#define CYGARC_REG_IMM_BR_BI           0x00000002       // burst inhibit
#define CYGARC_REG_IMM_BR_V            0x00000001       // valid bit

#define CYGARC_REG_IMM_OR_AM           0xffff8000       // address mask   
#define CYGARC_REG_IMM_OR_ATM          0x00007000       // address type mask
#define CYGARC_REG_IMM_OR_CSNT         0x00000800       // GPCM : chip select negatoion time
#define CYGARC_REG_IMM_OR_ACS_0        0x00000000       // GPCM : CS output immediately
#define CYGARC_REG_IMM_OR_ACS_4        0x00000400       // GPCM : CS output 1/4 clock cycle later
#define CYGARC_REG_IMM_OR_ACS_2        0x00000600       // GPCM : CS output 1/2 clock cycle later
#define CYGARC_REG_IMM_OR_SCY_MASK     0x000000f0       // cycle length in clocks
#define CYGARC_REG_IMM_OR_BSCY         0x0000000E       // burst cycle length in clocks
#define CYGARC_REG_IMM_OR_TRLX         0x00000001       // timing relaxed
#define CYGARC_REG_IMM_OR_EHTR         0x00000100       // extended hold time on read
#define CYGARC_REG_IMM_OR_SCY_SHIFT    4            

//-----------------------------------------------------------------------------
// Time base status and control (TBSCR)
#define CYGARC_REG_IMM_TBSCR_REFA      0x0080           // reference interrupt status A
#define CYGARC_REG_IMM_TBSCR_REFB      0x0040           // reference interrupt status B
#define CYGARC_REG_IMM_TBSCR_REFAE     0x0008           // reference interrupt enable A
#define CYGARC_REG_IMM_TBSCR_REFBE     0x0004           // reference interrupt enable B
#define CYGARC_REG_IMM_TBSCR_TBF       0x0002           // timebase freeze
#define CYGARC_REG_IMM_TBSCR_TBE       0x0001           // timebase enable
#define CYGARC_REG_IMM_TBSCR_IRQ0      0x8000           // highest interrupt level
#define CYGARC_REG_IMM_TBSCR_IRQMASK   0xff00           // irq priority mask

//-----------------------------------------------------------------------------
// Real time clock
#define CYGARC_REG_IMM_RTCSC_SEC       0x0080           // once per second interrupt
#define CYGARC_REG_IMM_RTCSC_ALR       0x0040           // alarm interrupt
#define CYGARC_REG_IMM_RTCSC_4M        0x0010           // source select
#define CYGARC_REG_IMM_RTCSC_SIE       0x0008           // second interrupt enable
#define CYGARC_REG_IMM_RTCSC_ALE       0x0004           // alarm interrupt enable
#define CYGARC_REG_IMM_RTCSC_RTF       0x0002           // real time clock freeze
#define CYGARC_REG_IMM_RTCSC_RTE       0x0001           // real time clock enable
#define CYGARC_REG_IMM_RTCSC_IRQ0      0x8000           // highest interrupt priority
#define CYGARC_REG_IMM_RTCSC_IRQMASK   0xff00           // irq priority mask

//-----------------------------------------------------------------------------
// Periodic interrupt status an control
#define CYGARC_REG_IMM_PISCR_PS        0x0080           // periodic interrupt status
#define CYGARC_REG_IMM_PISCR_PIE       0x0004           // periodic interrupt enable
#define CYGARC_REG_IMM_PISCR_PITF      0x0002           // periodic interrupt timer freeze
#define CYGARC_REG_IMM_PISCR_PTE       0x0001           // periodic timer enable
#define CYGARC_REG_IMM_PISCR_IRQ0      0x8000           // highest intetrupt priority
#define CYGARC_REG_IMM_PISCR_IRQMASK   0xff00           // irq priority mask

//-----------------------------------------------------------------------------
// Queued analog to digital convertor
#define CYGARC_REG_IMM_QUACR1_CIE1       0x8000
#define CYGARC_REG_IMM_QUACR1_PIE1       0x4000
#define CYGARC_REG_IMM_QUACR1_SSE1       0x2000
#define CYGARC_REG_IMM_QUACR1_MO1        0x1f00
#define CYGARC_REG_IMM_QUACR2_CIE2       0x8000
#define CYGARC_REG_IMM_QUACR2_PIE2       0x4000
#define CYGARC_REG_IMM_QUACR2_SSE2       0x2000
#define CYGARC_REG_IMM_QUACR2_MO2        0x1f00
#define CYGARC_REG_IMM_QUACR2_RESUME     0x0080
#define CYGARC_REG_IMM_QUACR2_BQ2        0x007f
#define CYGARC_REG_IMM_QUASR0_CF1        0x8000
#define CYGARC_REG_IMM_QUASR0_PF1        0x4000
#define CYGARC_REG_IMM_QUASR0_CF2        0x2000
#define CYGARC_REG_IMM_QUASR0_PF2        0x1000
#define CYGARC_REG_IMM_QUASR0_TOR1       0x0800
#define CYGARC_REG_IMM_QUASR0_TOR2       0x0400
#define CYGARC_REG_IMM_QUASR0_QS         0x03c0
#define CYGARC_REG_IMM_QUASR0_CWP        0x003f
#define CYGARC_REG_IMM_QUADC64INT_IRL1   0xf800
#define CYGARC_REG_IMM_QUADC64INT_IRL2   0x07c0
#define CYGARC_REG_IMM_QUADC64INT_IRL1_SHIFT 11
#define CYGARC_REG_IMM_QUADC64INT_IRL2_SHIFT  6

//-----------------------------------------------------------------------------
// PLL Change of lock
#define CYGARC_REG_IMM_COLIR_IRQ0      0x8000           // the highest interrupt priority
#define CYGARC_REG_IMM_COLIR_COLIRQ    0xff00           // interrupt priority mask
#define CYGARC_REG_IMM_COLIR_COLIS     0x0080           // change of lock detected
#define CYGARC_REG_IMM_COLIR_COLIE     0x0040           // change of lock interrupt enable

//-----------------------------------------------------------------------------
// SCI SPI registers
#define CYGARC_REG_IMM_SCCxR1_LOOPS     0x4000
#define CYGARC_REG_IMM_SCCxR1_WOMS      0x2000
#define CYGARC_REG_IMM_SCCxR1_ILT       0x1000
#define CYGARC_REG_IMM_SCCxR1_PT        0x0800
#define CYGARC_REG_IMM_SCCxR1_PE        0x0400
#define CYGARC_REG_IMM_SCCxR1_M         0x0200
#define CYGARC_REG_IMM_SCCxR1_WAKE      0x0100
#define CYGARC_REG_IMM_SCCxR1_TIE       0x0080
#define CYGARC_REG_IMM_SCCxR1_TCIE      0x0040
#define CYGARC_REG_IMM_SCCxR1_RIE       0x0020
#define CYGARC_REG_IMM_SCCxR1_ILIE      0x0010
#define CYGARC_REG_IMM_SCCxR1_TE        0x0008
#define CYGARC_REG_IMM_SCCxR1_RE        0x0004
#define CYGARC_REG_IMM_SCCxR1_RWU       0x0002
#define CYGARC_REG_IMM_SCCxR1_SBK       0x0001
#define CYGARC_REG_IMM_QSCI1CR_QTPNT    0xf000
#define CYGARC_REG_IMM_QSCI1CR_QTHFI    0x0800
#define CYGARC_REG_IMM_QSCI1CR_QBHFI    0x0400
#define CYGARC_REG_IMM_QSCI1CR_QTHEI    0x0200
#define CYGARC_REG_IMM_QSCI1CR_QBHEI    0x0100
#define CYGARC_REG_IMM_QSCI1CR_QTE      0x0040
#define CYGARC_REG_IMM_QSCI1CR_QRE      0x0020
#define CYGARC_REG_IMM_QSCI1CR_QTWE     0x0010
#define CYGARC_REG_IMM_QSCI1CR_QTSZ     0x000f
#define CYGARC_REG_IMM_SPCR1_SPE        0x8000
#define CYGARC_REG_IMM_SPCR1_DSCLK      0x7f00  
#define CYGARC_REG_IMM_SPCR1_DTL        0x00ff
#define CYGARC_REG_IMM_SPCR2_SPIFIE     0x8000
#define CYGARC_REG_IMM_SPCR2_WREN       0x4000
#define CYGARC_REG_IMM_SPCR2_WRT0       0x2000
#define CYGARC_REG_IMM_SPCR2_ENDQP      0x1f00
#define CYGARC_REG_IMM_SPCR2_NEWQP      0x001f
#define CYGARC_REG_IMM_SPCR3_LOOPQ      0x0400
#define CYGARC_REG_IMM_SPCR3_HMIE       0x0200
#define CYGARC_REG_IMM_SPCR3_HALT       0x0100
#define CYGARC_REG_IMM_SPCR3_SPSR       0x00ff
#define CYGARC_REG_IMM_SCxSR_TDRE       0x0100
#define CYGARC_REG_IMM_SCxSR_TC         0x0080
#define CYGARC_REG_IMM_SCxSR_RDRF       0x0040
#define CYGARC_REG_IMM_SCxSR_RAF        0x0020
#define CYGARC_REG_IMM_SCxSR_IDLE       0x0010
#define CYGARC_REG_IMM_SCxSR_OR         0x0008
#define CYGARC_REG_IMM_SCxSR_NF         0x0004
#define CYGARC_REG_IMM_SCxSR_FE         0x0002
#define CYGARC_REG_IMM_SCxSR_PF         0x0001
#define CYGARC_REG_IMM_QSCI1SR_QOR      0x1000
#define CYGARC_REG_IMM_QSCI1SR_QTHF     0x0800
#define CYGARC_REG_IMM_QSCI1SR_QBHF     0x0400
#define CYGARC_REG_IMM_QSCI1SR_QTHE     0x0200
#define CYGARC_REG_IMM_QSCI1SR_QBHE     0x0100
#define CYGARC_REG_IMM_QSCI1SR_QRPNT    0x00f0
#define CYGARC_REG_IMM_QSCI1SR_QRPEND   0x000f
#define CYGARC_REG_IMM_SPSR_SPCR3       0xff00
#define CYGARC_REG_IMM_SPSR_SPIF        0x0080
#define CYGARC_REG_IMM_SPSR_MODF        0x0040
#define CYGARC_REG_IMM_SPSR_HALTA       0x0020
#define CYGARC_REG_IMM_SPSR_CPTQ        0x001f
#define CYGARC_REG_IMM_QDSCI_IL_ILDSCI  0x1f00
#define CYGARC_REG_IMM_QDSCI_IL_ILDSCI_SHIFT 8
#define CYGARC_REG_IMM_QSPI_IL_ILQSPI   0x001f
#define CYGARC_REG_IMM_QSPI_IL_ILQSPI_SHIFT  0

//-----------------------------------------------------------------------------
// TPU register settings
#define CYGARC_REG_IMM_TICR_CIRL       0x0700
#define CYGARC_REG_IMM_TICR_CIRL_SHIFT      8
#define CYGARC_REG_IMM_TICR_ILBS       0x00c0
#define CYGARC_REG_IMM_TICR_ILBS_SHIFT      6

//-----------------------------------------------------------------------------
// TOUCAN registers
#define CYGARC_REG_IMM_CANCTRL0_BOFFMSK  0x8000
#define CYGARC_REG_IMM_CANCTRL0_ERRMSK   0x4000
#define CYGARC_REG_IMM_CANCTRL0_RXMOD    0x0c00
#define CYGARC_REG_IMM_CANCTRL0_TXMOD    0x0300
#define CYGARC_REG_IMM_CANCTRL0_CANCTLL1 0x00ff
#define CYGARC_REG_IMM_TCNMCR_STOP       0x8000
#define CYGARC_REG_IMM_TCNMCR_FRZ        0x4000
#define CYGARC_REG_IMM_TCNMCR_HALT       0x1000
#define CYGARC_REG_IMM_TCNMCR_NOTRDY     0x0800
#define CYGARC_REG_IMM_TCNMCR_WAKEMSK    0x0400
#define CYGARC_REG_IMM_TCNMCR_SOFTRST    0x0200
#define CYGARC_REG_IMM_TCNMCR_FRZACK     0x0100
#define CYGARC_REG_IMM_TCNMCR_SUPV       0x0080
#define CYGARC_REG_IMM_TCNMCR_SELFWAKE   0x0040
#define CYGARC_REG_IMM_TCNMCR_APS        0x0020
#define CYGARC_REG_IMM_TCNMCR_STOPACK    0x0010
#define CYGARC_REG_IMM_ESTAT_BOFFINT     0x0004
#define CYGARC_REG_IMM_ESTAT_ERRINT      0x0002
#define CYGARC_REG_IMM_ESTAT_WAKEINT     0x0001
#define CYGARC_REG_IMM_CANICR_IRL        0x0700
#define CYGARC_REG_IMM_CANICR_IRL_SHIFT       8
#define CYGARC_REG_IMM_CANICR_ILBS       0x00c0
#define CYGARC_REG_IMM_CANICR_ILBS_SHIFT      6

//-----------------------------------------------------------------------------
// MIOS registers
#define CYGARC_REG_IMM_MIOS1ER0_EN15     0x8000
#define CYGARC_REG_IMM_MIOS1ER0_EN14     0x4000
#define CYGARC_REG_IMM_MIOS1ER0_EN13     0x2000
#define CYGARC_REG_IMM_MIOS1ER0_EN12     0x1000
#define CYGARC_REG_IMM_MIOS1ER0_EN11     0x0800
#define CYGARC_REG_IMM_MIOS1ER0_EN6      0x0040
#define CYGARC_REG_IMM_MIOS1ER0_EN3      0x0008
#define CYGARC_REG_IMM_MIOS1ER0_EN2      0x0004
#define CYGARC_REG_IMM_MIOS1ER0_EN1      0x0002
#define CYGARC_REG_IMM_MIOS1ER0_EN0      0x0001
#define CYGARC_REG_IMM_MIOS1ER1_EN31     0x8000
#define CYGARC_REG_IMM_MIOS1ER1_EN30     0x4000
#define CYGARC_REG_IMM_MIOS1ER1_EN29     0x2000
#define CYGARC_REG_IMM_MIOS1ER1_EN28     0x1000
#define CYGARC_REG_IMM_MIOS1ER1_EN27     0x0800
#define CYGARC_REG_IMM_MIOS1ER1_EN22     0x0040
#define CYGARC_REG_IMM_MIOS1ER1_EN19     0x0008
#define CYGARC_REG_IMM_MIOS1ER1_EN18     0x0004
#define CYGARC_REG_IMM_MIOS1ER1_EN17     0x0002
#define CYGARC_REG_IMM_MIOS1ER1_EN16     0x0001
#define CYGARC_REG_IMM_MIOS1SR0_FL15     0x8000
#define CYGARC_REG_IMM_MIOS1SR0_FL14     0x4000
#define CYGARC_REG_IMM_MIOS1SR0_FL13     0x2000
#define CYGARC_REG_IMM_MIOS1SR0_FL12     0x1000
#define CYGARC_REG_IMM_MIOS1SR0_FL11     0x0800
#define CYGARC_REG_IMM_MIOS1SR0_FL6      0x0040
#define CYGARC_REG_IMM_MIOS1SR0_FL3      0x0008
#define CYGARC_REG_IMM_MIOS1SR0_FL2      0x0004
#define CYGARC_REG_IMM_MIOS1SR0_FL1      0x0002
#define CYGARC_REG_IMM_MIOS1SR0_FL0      0x0001
#define CYGARC_REG_IMM_MIOS1SR1_FL31     0x8000
#define CYGARC_REG_IMM_MIOS1SR1_FL30     0x4000
#define CYGARC_REG_IMM_MIOS1SR1_FL29     0x2000
#define CYGARC_REG_IMM_MIOS1SR1_FL28     0x1000
#define CYGARC_REG_IMM_MIOS1SR1_FL27     0x0800
#define CYGARC_REG_IMM_MIOS1SR1_FL22     0x0040
#define CYGARC_REG_IMM_MIOS1SR1_FL19     0x0008
#define CYGARC_REG_IMM_MIOS1SR1_FL18     0x0004
#define CYGARC_REG_IMM_MIOS1SR1_FL17     0x0002
#define CYGARC_REG_IMM_MIOS1SR1_FL16     0x0001
#define CYGARC_REG_IMM_MIOS1LVL_LVL      0x0700