ts1000.s

来自「eCos操作系统源码」· S 代码 · 共 610 行 · 第 1/2 页

	/*
	 * Clear SERC & ALR. RTC runs on freeze. Enable RTC.
	 */
	li	r3,0x0000            // FIXME:   should this be 0x0000 or 0x00C3
	sth	r3,RTCSC(r4)

	/*
	 * Clear periodic timer interrupt status.
	 * Enable periodic timer and stop it on freeze.
	 */
        li	r3,0x0001            // FIXME:   should this be 0x0001 or 0x0083
        sth	r3,PISCR(r4)

	LED( 0x02 )
	
	/*
	 * Perform UPM programming by writing to its 64 RAM locations.
	 * Note that UPM initialization must be done before the Bank Register
	 * initialization. Otherwise, system may hang when writing to Bank
	 * Registers in certain cases.
	 */
#ifdef CYGPRI_DO_PROGRAM_UPMS
	lwi	r5,__upmtbl_start
	lwi	r6,__upmtbl_end
	sub	r7,r6,r5      /* size of table */ 
	srawi	r7,r7,2       /* in words */
        
        lwi	r6,0x00800000     /* Command - OP=Write, UPMB, MAD=0 */
        or      r7,r7,r6
    1:
        lwz	r3,0(r5)      /* get data from table */
        stw	r3,MDR(r4)    /* store the data to MD register */
        stw	r6,MCR(r4)    /* issue command to MCR register */
        addi	r5,r5,4       /* next entry in the table */
        addi	r6,r6,1       /* next MAD address */
        cmpw	r6,r7         /* done yet ? */
        blt	1b
#endif // CYGPRI_DO_PROGRAM_UPMS
	
	LED( 0x03 )

	/*
	 * Set refresh timer prescaler to divide by 8.
	 */
        li	r3,PTP_DIV32
        sth	r3,MPTPR(r4)

        /*
	 * See Table 15-16 MPC860 User's Manual.
	 *
// Set the value of Machine A Mode Register (MAMR) to $5E802114.
// 	Field PTA (bits 0-7) = 94
// 	Field PTAE (bit 8) = 1
// 	Field AMA (bits 9-11) = 0
// 	Field Reserved (bit 12) = 0
// 	Field DSA (bits 13-14) = 0
// 	Field Reserved (bit 15) = 0
// 	Field G0CLA (bits 16-18) = 1
// 	Field GPL_A4DIS (bit 19) = 0
// 	Field RLFA (bits 20-23) = 1
// 	Field WLFA (bits 24-27) = 1
// 	Field TLFA (bits 28-31) = 4
	 */
        lwi     r3,0x00802114|(MAMR_PTA<<24)
        stw	r3,MAMR(r4)
        stw	r3,MBMR(r4)

	/*
	 * Base Register initialization.
	 */

//
// Memory map (device addressing) layout
//
        bl      10f
mc_regs:
// CS0 - FLASH - 0xFE000000..0xFE7FFFFF, 9 wait states, no bursting
        _OR_GPCM(OR0, 0xFF800000, _CSNT_1, _ACS_2, \
	         _BIH_1, _SCY_9, _SETA_0, _TRLX_1, _EHTR_1)
        _BR(BR0, 0xFE000000, _PS_16, _MS_GPCM, 1)

// CS1 - DRAM - 0x00000000..0x00FFFFFF,
        _BR(BR1, 0x00000000, _PS_32, _MS_UPMB, 1)
        _OR_UPM(OR1, 0xFF000000, _SAM_1, _G5LA_0, _G5LS_0, _BIH_0)
        
// CS2 - FPGA Loading - 0x80020000..0x80027FFF, 7 wait states, no bursting
        _BR(BR2, 0x80020000, _PS_32, _MS_GPCM, 1)
        _OR_GPCM(OR2, 0xFFFF8000, _CSNT_1, _ACS_2, \
	         _BIH_1, _SCY_7, _SETA_0, _TRLX_1, _EHTR_1)
        
// CS3 - FPGA - 0x80030000..0x80037FFF, 7 wait states, no bursting
        _OR_GPCM(OR3, 0xFFFF8000, _CSNT_1, _ACS_2, \
	         _BIH_1, _SCY_7, _SETA_0, _TRLX_1, _EHTR_1)	
        _BR(BR3, 0x80030000, _PS_32, _MS_GPCM, 1)
        
// CS4 - DS3 - 0x80040000..0x80047FFF, 7 wait states, no bursting
        _OR_GPCM(OR4, 0xFFFF8000, _CSNT_1, _ACS_2, \
	         _BIH_1, _SCY_7, _SETA_0, _TRLX_1, _EHTR_1)
        _BR(BR4, 0x80040000, _PS_32, _MS_GPCM, 1)
        
// CS5 - DS1 - 0x80050000..0x80057FFF, 7 wait states, no bursting
        _OR_GPCM(OR5, 0xFFFF8000, _CSNT_1, _ACS_2, \
	         _BIH_1, _SCY_7, _SETA_0, _TRLX_1, _EHTR_1)
        _BR(BR5, 0x80050000, _PS_32, _MS_GPCM, 1)
	
        .long   0       // End of table               

//
// Program memory controller registers (using table above)
//
10:     mflr    r3              // Points to table
        subi    r3,r3,4
20:     lwzu    r5,4(r3)        // Next address
        cmpi    0,r5,0
        beq     30f             // done?
        lwzu    r6,4(r3)        // value
	lwzu	r7,4(r3)	// second part of address/value pair
	lwzu	r8,4(r3)
        stw     r6,0(r5)	// store pair in order
	stw	r8,0(r7)
        b       20b
30:
	        
	/*
	 *  SYSTEM CLOCK CONTROL REGISTER
// Set the value of System Clock and Reset Control Register (SCCR) to $00400000.
// 	Field Reserved (bit 0) = 0
// 	Field COM (bits 1-2) = 0
// 	Field Reserved (bits 3-5) = 0
// 	Field TBS (bit 6) = 0
// 	Field RTDIV (bit 7) = 0
// 	Field RTSEL (bit 8) = 0
// 	Field CRQEN (bit 9) = 1
// 	Field PRQEN (bit 10) = 0
// 	Field Reserved (bits 11-12) = 0
// 	Field EBDF (bits 13-14) = 0
// 	Field Reserved (bits 15-16) = 0
// 	Field DFSYNC (bits 17-18) = 0
// 	Field DFBRG (bits 19-20) = 0
// 	Field DFNL (bits 21-23) = 0
// 	Field DFNH (bits 24-26) = 0
// 	Field Reserved (bits 27-31) = 0
	 */
	lwi	r3,0x00400000
	stw	r3,SCCR(r4)
        
	LED( 0x04 )

	/*
	 *  PLL, LOW POWER, AND RESET CONTROL REGISTER
// Set the value of PLL, Low Power and Reset Control Register (PLPRCR) to $00C04000.
// 	Field MF (bits 0-11) = 12
// 	Field Reserved (bits 12-15) = 0
// 	Field SPLSS (bit 16) = 0
// 	Field TEXPS (bit 17) = 1
// 	Field Reserved (bit 18) = 0
// 	Field TMIST (bit 19) = 0
// 	Field Reserved (bit 20) = 0
// 	Field CSRC (bit 21) = 0
// 	Field LPM (bits 22-23) = 0
// 	Field CSR (bit 24) = 0
// 	Field LOLRE (bit 25) = 0
// 	Field FIOPD (bit 26) = 0
// 	Field Reserved (bits 27-31) = 0
	 */
	lwi	r3,0x04000|(PLPRCR_PTX<<20)
	stw	r3,PLPRCR(r4)

	lwi	r3,0x40000
	mtctr	r3
10:	nop
	bdnz	10b

	/* SDRAM Initialization Sequence, UPMB, CS1 */
	li	r3,0
	stw	r3,MAR(r4)

	lwi 	r3,0x80802115;	/* run precharge from loc 21 (0x15) */
  	stw	r3,MCR(r4)

	lwi	r3,0x80802830;	/* run refresh 8 times */
   	stw	r3,MCR(r4)
	
	lwi	r3,0x22<<2;	// Mode register setting
   	stw	r3,MAR(r4)

       	lwi	r3,0x80802116;	/* run MRS pattern from loc 22 (0x16) */
   	stw	r3,MCR(r4)

	# mask interrupt sources in the SIU
	lis	r2,0
	lwi	r3,CYGARC_REG_IMM_SIMASK
	stw	r2,0(r3)

	# set the decrementer to maxint
	lwi	r2,0
	not	r2,r2
	mtdec	r2
	
	# and enable the timebase and decrementer to make sure
	li	r2,1				# TBEnable and not TBFreeze
	lwi	r3,CYGARC_REG_IMM_TBSCR
	sth	r2,0(r3)

	LED( 0x05 ) 

#ifdef CYG_HAL_STARTUP_ROM
	# move return address to where the ROM is
	mflr	r3
        lwi     r4,0x00FFFFFF        // CAUTION!! Assumes only low 16M for ROM
        and     r3,r3,r4
	oris	r3,r3,CYGMEM_REGION_rom>>16
	mtlr	r3
#endif

#ifdef CYG_HAL_STARTUP_ROMRAM
        // Copy image from ROM to RAM
        LED(0x06)
        lwi     r4,0xFE000000
        lwi     r5,0x01FFFFFF   // ROM/FLASH base
        and     r3,r30,r5       // segment relative
        lwi     r30,_hal_hardware_init_done
        sub     r6,r3,r30       // Absolute address
        add     r6,r6,r4        // FLASH address
        lwi     r7,0            // where to copy to
        lwi     r8,__ram_data_end
10:     lwz     r5,0(r6)
        stw     r5,0(r7)
        addi    r6,r6,4
        addi    r7,r7,4
        cmplw   r7,r8
        bne     10b
#endif                

        LED(0x0F)
	
        mtlr    r30             // Restore original link address
	blr
FUNC_END( hal_hardware_init )


#ifdef CYGPRI_DO_PROGRAM_UPMS
# -------------------------------------------------------------------------
# this table initializes the User Programmable Machine (UPM) nastiness
# in the QUICC to control DRAM timing.

__upmtbl_start:

// UPM 0x00: single read
       .long   0x0f0dfc04, 0x0ffffc04, 0x00bf7c04, 0x0ff5fc00
       .long   0x1ffffc05, 0xfffffc04, 0xfffffc04, 0xfffffc04
// UPM 0x08: burst read
       .long   0x0f0dfc04, 0x0ffffc04, 0x00bf7c04, 0x00fffc00
       .long   0x00fffc00, 0x00fffc00, 0x0ff5fc00, 0x1ffffc05
       .long   0xfffffc04, 0xfffffc04, 0xfffffc04, 0xfffffc04
       .long   0xfffffc04
// UPM 0x15: initial precharge cycles
       .long   0x1ff5fc35
// UPM 0x16: program mode register
       .long   0xefcabc34, 0x1f357c35 // 0x1fb57c35 or 0xfffffc04
// UPM 0x18: single write
       .long   0x0f0dfc04, 0x0ffffc00, 0x00b77c04, 0x0ffffc04
       .long   0x0ff5fc04, 0x1ffffc05, 0xfffffc04, 0xfffffc04
// UPM 0x20: burst write
       .long   0x0f0dfc04, 0x0ffffc00, 0x00b77c00, 0x00fffc00
       .long   0x00fffc00, 0x00fffc04, 0x0ffffc04, 0x0ff5fc04
       .long   0x1ffffc05, 0xfffffc04, 0xfffffc04, 0xfffffc04
       .long   0xfffffc04, 0xfffffc04, 0xfffffc04, 0xfffffc04
// UPM 0x30: refresh
       .long   0x0ff5fc00, 0x0ffffc00, 0x0ffd7c80, 0x0ffffc00
       .long   0x0ffffc00, 0x0ffffc80, 0x3ffffc07, 0xfffffc04
       .long   0xfffffc04, 0xfffffc04, 0xfffffc04, 0xfffffc04
// UPM 0x3C: exception
       .long   0xfffffc27, 0xfffffc04, 0xfffffc04, 0xfffffc04

__upmtbl_end:
#endif // CYGPRI_DO_PROGRAM_UPMS
	
FUNC_START(hal_ts1000_set_led)
	lwi     r4,CYGARC_REG_IMM_BASE  # base address of control registers
        lhz     r5,PADAT(r4)         
        andi.   r5,r5,(~0x3C&0xFFFF)
	andi.	r3,r3,0x0F
        slwi    r3,r3,2
        or      r5,r5,r3
        sth     r5,PADAT(r4)         
	lwi	r5,_hold_led
	stw	r3,0(r5)
	blr
FUNC_END(hal_ts1000_set_led)
	.data
_hold_led:	
	.long	0
	.text	
	
FUNC_START(hal_ts1000_get_led)
	lwi	r5,_hold_led
	lwz	r3,0(r5)
	blr
FUNC_END(hal_ts1000_get_led)


#------------------------------------------------------------------------------
# end of ts1000.S