quicc2_diag.c

来自「eCos操作系统源码」· C语言 代码 · 共 558 行 · 第 1/2 页

    }
    rxbd--;
    rxbd->ctrl   |= _BD_CTL_Wrap;

    // setup TX buffer descriptor
    txbd = (struct cp_bufdesc *)((char *)IMM + txbase);
    txbd->length = 1;
    txbd->buffer = ((char *)IMM + (txbase+(info->Txnum*sizeof(struct cp_bufdesc))));
    txbd->ctrl   = _BD_CTL_Wrap;

    // Set the baud rate generator.  Note: on the MPC8xxx, 
    // there are a number of BRGs, but the usage/layout is
    // somewhat restricted, so we rely on a fixed mapping.
    // See the setup in the platform init code for details.
    *(unsigned long *)((char *)IMM + info->brg) = 0x00010000 | (UART_BIT_RATE(UART_BAUD_RATE) << 1);

    // Rx, Tx function codes (used for access)
    pram->rfcr = 0x18;
    pram->tfcr = 0x18;
    regs->psmr = 0xB000;

    // Pointers to Rx & Tx buffer descriptor rings
    pram->rbase = rxbase;
    pram->tbase = txbase;

    // Max receive buffer length
    pram->mrblr = 1;
   
    // Mode register for 8N1
    regs->gsmr_h = 0x00000060;
    regs->gsmr_l = 0x00028004;  

    // Clear events
    regs->scce = ALL_ONES;
    regs->sccm = SCCE_Rx;

    // Init channel
    while ((IMM->cpm_cpcr & CPCR_FLG) != READY_TO_RX_CMD); 
    IMM->cpm_cpcr = cpm_page | 
        CPCR_INIT_TX_RX_PARAMS |
        CPCR_FLG;                 /* ISSUE COMMAND */
    while ((IMM->cpm_cpcr & CPCR_FLG) != READY_TO_RX_CMD); 

    /*-------------------------------------------------------------*/
    /* Set the ENT/ENR bits in the GSMR -- Enable Transmit/Receive */
    /*-------------------------------------------------------------*/

    regs->gsmr_l |= GSMR_L1_ENT | GSMR_L1_ENR;
#if defined(CYGDBG_HAL_DEBUG_GDB_BREAK_SUPPORT) \
    || defined(CYGDBG_HAL_DEBUG_GDB_CTRLC_SUPPORT)
    // Fill out the control Character Table.  Make the first entry 
    // an end of table line. 
    // cc[0] = 0x4003 ==> reject if char = 0x3, write to RCCR
    pram->SpecificProtocol.u.cc[0] = 0x4003;
    {
        int i;
        for (i = 0; i < 8; i++){
            pram->SpecificProtocol.u.cc[i] = 0x8000;
        }
    }
    
    pram->SpecificProtocol.u.rccm  = 0xc000;
#endif
}

static void
cyg_hal_plf_smcx_init_channel(struct port_info *info, int cpm_page)
{
    unsigned int rxbase, txbase;
    int i;
    struct cp_bufdesc *rxbd, *txbd;
    volatile struct smc_regs_8260 *regs = (volatile struct smc_regs_8260*)((char *)IMM + info->regs);
    t_Smc_Pram *uart_pram = (t_Smc_Pram *)((char *)IMM + info->pram);

    if (info->init) return;
    info->init = 1;

    // Make sure device is stopped
    while ((IMM->cpm_cpcr & CPCR_FLG) != READY_TO_RX_CMD); 
    IMM->cpm_cpcr = cpm_page |
        CPCR_STOP_TX |
        CPCR_FLG;             /* ISSUE COMMAND */
    while ((IMM->cpm_cpcr & CPCR_FLG) != READY_TO_RX_CMD); 

    // Allocate buffer descriptors + buffers (adjacent to descriptors)
    rxbase = _mpc8xxx_allocBd(sizeof(struct cp_bufdesc)*info->Rxnum + info->Rxnum);
    txbase = _mpc8xxx_allocBd(sizeof(struct cp_bufdesc)*info->Txnum + info->Txnum);

    // setup RX buffer descriptors 
    rxbd = (struct cp_bufdesc *)((char *)IMM + rxbase);
    info->next_rxbd = rxbd;
    for (i = 0;  i < info->Rxnum;  i++) {
        rxbd->length = 0;
        rxbd->buffer = ((char *)IMM + (rxbase+(info->Rxnum*sizeof(struct cp_bufdesc))))+i;
        rxbd->ctrl   = _BD_CTL_Ready | _BD_CTL_Int;
        rxbd++;
    }
    rxbd--;
    rxbd->ctrl   |= _BD_CTL_Wrap;

    // setup TX buffer descriptor
    txbd = (struct cp_bufdesc *)((char *)IMM + txbase);
    txbd->length = 1;
    txbd->buffer = ((char *)IMM + (txbase+(info->Txnum*sizeof(struct cp_bufdesc))));
    txbd->ctrl   = _BD_CTL_Wrap;

    // Set the baud rate generator.  Note: on the MPC8xxx, 
    // there are a number of BRGs, but the usage/layout is
    // somewhat restricted, so we rely on a fixed mapping.
    // See the setup in the platform init code for details.
    *(unsigned long *)((char *)IMM + info->brg) = 0x00010000 | (UART_BIT_RATE(UART_BAUD_RATE) << 1);

    // Rx, Tx function codes (used for access)
    uart_pram->rfcr = 0x18;
    uart_pram->tfcr = 0x18;

    // Pointers to Rx & Tx buffer descriptor rings
    uart_pram->rbase = rxbase;
    uart_pram->tbase = txbase;

    // Max receive buffer length
    uart_pram->mrblr = 1;
   
    // Mode register for 8N1
    regs->smc_smcmr = 0x4823;

    // Clear events
    regs->smc_smce = 0xFF;
    regs->smc_smcm = SMCE_Rx;

    // Init channel
    while ((IMM->cpm_cpcr & CPCR_FLG) != READY_TO_RX_CMD); 
    IMM->cpm_cpcr = cpm_page | 
        CPCR_INIT_TX_RX_PARAMS |
        CPCR_FLG;                 /* ISSUE COMMAND */
    while ((IMM->cpm_cpcr & CPCR_FLG) != READY_TO_RX_CMD); 
}

static void
cyg_hal_plf_serial_putc(void* __ch_data, cyg_uint8 ch)
{
    volatile struct cp_bufdesc *bd;
    struct port_info *info = (struct port_info *)__ch_data;
    volatile t_Scc_Pram *uart_pram = (volatile t_Scc_Pram *)((char *)IMM + info->pram);
    int cache_state;

    /* tx buffer descriptor */
    bd = (struct cp_bufdesc *)((char *)IMM + uart_pram->tbptr);
    while (bd->ctrl & _BD_CTL_Ready) ;  // Wait for buffer free
    if (bd->ctrl & _BD_CTL_Int) {
        // This buffer has just completed interrupt output.  Reset bits
        bd->ctrl &= ~_BD_CTL_Int;
    }
    bd->length = 1;
    bd->buffer[0] = ch;

    // Flush cache if necessary - buffer may be in cacheable memory
    HAL_DCACHE_IS_ENABLED(cache_state);
    if (cache_state) {
      HAL_DCACHE_FLUSH(bd->buffer, 1);
    }

    bd->ctrl      |= _BD_CTL_Ready;
    while (bd->ctrl & _BD_CTL_Ready) ;  // Wait for buffer free
}

static cyg_bool
cyg_hal_plf_serial_getc_nonblock(void* __ch_data, cyg_uint8* ch)
{
    volatile struct cp_bufdesc *bd;
    struct port_info *info = (struct port_info *)__ch_data;
    volatile t_Scc_Pram *uart_pram = (volatile t_Scc_Pram *)((char *)IMM + info->pram);
    int cache_state;

    /* rx buffer descriptor */
    bd = info->next_rxbd;

    if (bd->ctrl & _BD_CTL_Ready)
        return false;

    *ch = bd->buffer[0];

    bd->length = 0;
    bd->buffer[0] = '\0';
    bd->ctrl |= _BD_CTL_Ready;
    if (bd->ctrl & _BD_CTL_Wrap) {
        bd = (struct cp_bufdesc *)((char *)IMM + uart_pram->rbase);
    } else {
        bd++;
    }
    info->next_rxbd = bd;

    // Note: the MPC8xxx does not seem to snoop/invalidate the data cache properly!
    HAL_DCACHE_IS_ENABLED(cache_state);
    if (cache_state) {
        HAL_DCACHE_INVALIDATE(bd->buffer, uart_pram->mrblr);  // Make sure no stale data
    }

    return true;
}

static cyg_uint8
cyg_hal_plf_serial_getc(void* __ch_data)
{
    cyg_uint8 ch;
    while(!cyg_hal_plf_serial_getc_nonblock(__ch_data, &ch));
    return ch;
}

static void
cyg_hal_plf_serial_write(void* __ch_data, const cyg_uint8* __buf, 
                         cyg_uint32 __len)
{
    while(__len-- > 0)
        cyg_hal_plf_serial_putc(__ch_data, *__buf++);
}

static void
cyg_hal_plf_serial_read(void* __ch_data, cyg_uint8* __buf, cyg_uint32 __len)
{
    while(__len-- > 0)
        *__buf++ = cyg_hal_plf_serial_getc(__ch_data);
}

cyg_int32 msec_timeout = 1000;

static cyg_bool
cyg_hal_plf_serial_getc_timeout(void* __ch_data, cyg_uint8* ch)
{
    int delay_count = msec_timeout * 10; // delay in .1 ms steps
    cyg_bool res;

    for(;;) {
        res = cyg_hal_plf_serial_getc_nonblock(__ch_data, ch);
        if (res || 0 == delay_count--)
            break;
        
        CYGACC_CALL_IF_DELAY_US(100);
    }
    return res;
}

static int
cyg_hal_plf_serial_control(void *__ch_data, __comm_control_cmd_t __func, ...)
{
    int ret = 0;
    struct port_info *info = (struct port_info *)__ch_data;

    switch (__func) {
    case __COMMCTL_IRQ_ENABLE:
        HAL_INTERRUPT_UNMASK(info->intnum);
        info->irq_state = 1;
        break;
    case __COMMCTL_IRQ_DISABLE:
        ret = info->irq_state;
        info->irq_state = 0;
        HAL_INTERRUPT_MASK(info->intnum);
        break;
    case __COMMCTL_DBG_ISR_VECTOR:
        ret = info->intnum;
        break;
    case __COMMCTL_SET_TIMEOUT:
    {
        va_list ap;
        va_start(ap, __func);

        ret = msec_timeout;
        msec_timeout = va_arg(ap, cyg_uint32);

        va_end(ap);
    }        
    default:
        break;
    }
    return ret;
}

// EOF hal_aux.c