hal_aux.c

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//=============================================================================
//
//      hal_aux.c
//
//      HAL auxiliary objects and code; per platform
//
//=============================================================================
//####ECOSGPLCOPYRIGHTBEGIN####
// -------------------------------------------
// This file is part of eCos, the Embedded Configurable Operating System.
// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
// Copyright (C) 2002, 2003 Gary Thomas
//
// eCos is free software; you can redistribute it and/or modify it under
// the terms of the GNU General Public License as published by the Free
// Software Foundation; either version 2 or (at your option) any later version.
//
// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or
// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
// for more details.
//
// You should have received a copy of the GNU General Public License along
// with eCos; if not, write to the Free Software Foundation, Inc.,
// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
//
// As a special exception, if other files instantiate templates or use macros
// or inline functions from this file, or you compile this file and link it
// with other works to produce a work based on this file, this file does not
// by itself cause the resulting work to be covered by the GNU General Public
// License. However the source code for this file must still be made available
// in accordance with section (3) of the GNU General Public License.
//
// This exception does not invalidate any other reasons why a work based on
// this file might be covered by the GNU General Public License.
//
// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
// at http://sources.redhat.com/ecos/ecos-license/
// -------------------------------------------
//####ECOSGPLCOPYRIGHTEND####
//=============================================================================
//#####DESCRIPTIONBEGIN####
//
// Author(s):   hmt
// Contributors:hmt, gthomas
// Date:        1999-06-08
// Purpose:     HAL aux objects: startup tables.
// Description: Tables for per-platform initialization
//
//####DESCRIPTIONEND####
//
//=============================================================================

#include <pkgconf/hal.h>
#include <cyg/hal/hal_mem.h>            // HAL memory definitions
#include <cyg/infra/cyg_type.h>
#include <cyg/hal/mpc8xxx.h>            // For IMM structures
#include <cyg/hal/hal_if.h>
#include <cyg/hal/hal_intr.h>

// FIXME

static __inline__ unsigned long
_le32(unsigned long val)
{
    return (((val & 0x000000FF) << 24) |
            ((val & 0x0000FF00) <<  8) |
            ((val & 0x00FF0000) >>  8) |
            ((val & 0xFF000000) >> 24));
}

static __inline__ unsigned short
_le16(unsigned short val)
{
    return (((val & 0x000000FF) << 8) |
            ((val & 0x0000FF00) >> 8));
}

#define HAL_WRITE_UINT32LE(_addr_, _val_) \
  HAL_WRITE_UINT32(_addr_, _le32(_val_))
#define HAL_WRITE_UINT16LE(_addr_, _val_) \
  HAL_WRITE_UINT16(_addr_, _le16(_val_))
#define HAL_WRITE_UINT8LE(_addr_, _val_) \
  HAL_WRITE_UINT8(_addr_, _val_)
#define HAL_READ_UINT32LE(_addr_, _val_)        \
  {                                             \
      HAL_READ_UINT32(_addr_, _val_);           \
      _val_ = _le32(_val_);                     \
  }
#define HAL_READ_UINT16LE(_addr_, _val_)        \
  {                                             \
      HAL_READ_UINT16(_addr_, _val_);           \
      _val_ = _le16(_val_);                     \
  }
#define HAL_READ_UINT8LE(_addr_, _val_)        \
  HAL_READ_UINT8(_addr_, _val_)

// FIXME

// The memory map is weakly defined, allowing the application to redefine
// it if necessary. The regions defined below are the minimum requirements.
CYGARC_MEMDESC_TABLE CYGBLD_ATTRIB_WEAK = {
    // Mapping for the Rattler board
    CYGARC_MEMDESC_CACHE( 0x00000000, 0x01000000 ), // Main memory 60x SDRAM
    CYGARC_MEMDESC_CACHE( 0xFE000000, 0x00800000 ), // ROM region
    CYGARC_MEMDESC_NOCACHE( 0x80000000, 0x00100000 ), // Extended I/O
    CYGARC_MEMDESC_NOCACHE( 0xFF000000, 0x00100000 ), // IMMR registers

    CYGARC_MEMDESC_TABLE_END
};

//--------------------------------------------------------------------------
// Platform init code.
void
hal_platform_init(void)
{
#ifndef CYGSEM_HAL_USE_ROM_MONITOR
    volatile t_PQ2IMM  *IMM = (volatile t_PQ2IMM *)CYGARC_IMM_BASE;
    cyg_bool old_board_layout = *(unsigned long *)0xFE0000FC == 0;

    // Configure the I/O pins used by this board
    //   + = PARx = 0, PSORx = 0, PDIRx = 0
    //   A = PARX = 1, PSORx = 0, PDIRx = 0
    //   B = PARX = 1, PSORx = 1, PDIRx = 0
    //   C = PARX = 1, PSORx = 0, PDIRx = 1
    //   D = PARX = 1, PSORx = 1, PDIRx = 1

    // Port A
    //             1111111111222222222233
    //   01234567890123456789012345678901
    //   _______________________________________
    //                                  B  FCC1 - COL/MII
    //                                 B-  FCC1 - SRC/MII
    //                                D--  FCC1 - TX_ER/MII
    //                               D---  FCC1 - TX_EN/MII
    //                              B----  FCC1 - RX_DV/MII
    //                             B-----  FCC1 - RX_ER/MII
    //                            +------
    //                           +-------
    //                          +--------
    //                         +---------
    //                        C----------  FCC1 - TX[3]/MII
    //                       C-----------  FCC1 - TX[2]/MII
    //                      C------------  FCC1 - TX{1]/MII
    //                     C-------------  FCC1 - TX[0]/MII
    //                    A--------------  FCC1 - RX[3]/MII
    //                   A---------------  FCC1 - RX[2]/MII
    //                  A----------------  FCC1 - RX[1]/MII
    //                 A-----------------  FCC1 - RX[0]/MII
    //                +------------------
    //               +-------------------
    //              +--------------------
    //             +---------------------
    //            +----------------------
    //           +-----------------------
    //          +------------------------
    //         +-------------------------
    //        +--------------------------
    //       +---------------------------
    //      +----------------------------
    //     +-----------------------------  LED2
    //    +------------------------------  LED1
    //   +-------------------------------  LED0
    //   ++++ ++++ ++++ ++AA AACC CC++ ++BB DDBB
    //   0000 0000 0000 0011 1111 1100 0011 1111 PAR
    //   0000 0000 0000 0000 0000 0000 0011 1111 SOR
    //   0000 0000 0000 0000 0011 1100 0000 1100 DIR
    IMM->io_regs[PORT_A].ppar = 0x0003FC3F;
    IMM->io_regs[PORT_A].psor = 0x0000003F;
    IMM->io_regs[PORT_A].pdir = 0xE0003C0C;
    IMM->io_regs[PORT_A].podr = 0x00000000;

    // Port B
    //             1111111111222222222233
    //   01234567890123456789012345678901
    //   ________________________________
    //                                  C FCC2 - TX_ER
    //                                 A- FCC2 - RX_DV
    //                                D-- FCC2 - TX_EN
    //                               A--- FCC2 - RX_ER
    //                              A---- FCC2 - COL
    //                             A----- FCC2 - CRS
    //                            C------ FCC2 - TxD[3]
    //                           C------- FCC2 - TxD[2]
    //                          C-------- FCC2 - TxD[1]
    //                         C--------- FCC2 - TxD[0]
    //                        A---------- FCC2 - RxD[0]
    //                       A----------- FCC2 - RxD[1]
    //                      A------------ FCC2 - RxD[2]
    //                     A------------- FCC2 - RxD[3]
    //                    +--------------
    //                   +---------------
    //                  +----------------
    //                 +-----------------
    //                +------------------
    //               +-------------------
    //              +--------------------
    //             +---------------------
    //            +----------------------
    //           +-----------------------
    //          +------------------------
    //         +-------------------------
    //        +--------------------------
    //       +---------------------------
    //      +----------------------------
    //     +-----------------------------
    //    +------------------------------
    //   +-------------------------------
    //   ++++ ++++ ++++ ++++ ++AA AACC CCAA ADAC
    //   0000 0000 0000 0000 0011 1111 1111 1111 PAR
    //   0000 0000 0000 0000 0000 0000 0000 0100 SOR
    //   0000 0000 0000 0000 0000 0011 1100 0101 DIR
    IMM->io_regs[PORT_B].ppar = 0x00003FFF;
    IMM->io_regs[PORT_B].psor = 0x00000004;
    IMM->io_regs[PORT_B].pdir = 0x000003C5;
    IMM->io_regs[PORT_B].podr = 0x00000000;

    // Port C
    //             1111111111222222222233
    //   01234567890123456789012345678901
    //   ________________________________
    //                                  +
    //                                 +-