excalibur.h

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#ifndef CYGONCE_EXCALIBUR_H
#define CYGONCE_EXCALIBUR_H

//=============================================================================
//
//      excalibur.h
//
//      Platform specific support (register layout, etc)
//
//=============================================================================
//####ECOSGPLCOPYRIGHTBEGIN####
// -------------------------------------------
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// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
//
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// WARRANTY; without even the implied warranty of MERCHANTABILITY or
// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
// for more details.
//
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// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
//
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// or inline functions from this file, or you compile this file and link it
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// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
// at http://sources.redhat.com/ecos/ecos-license/
// -------------------------------------------
//####ECOSGPLCOPYRIGHTEND####
//=============================================================================
//#####DESCRIPTIONBEGIN####
//
// Author(s):    jskov
// Contributors: jskov
// Date:         2001-08-06
// Purpose:      Altera/EXCALIBUR platform specific support routines
// Description: 
// Usage:        #include <cyg/hal/excalibur.h>
//
//####DESCRIPTIONEND####
//
//=============================================================================

#include <pkgconf/hal_arm_arm9_excalibur.h>

#define EXCALIBUR_BASE         EXCALIBUR_REGS_PHYS_BASE

//-----------------------------------------------------------------------------
// Boot control
// Note: this register is actually write-bit-to-clear-it
#define EXCALIBUR_BOOT_CR      (EXCALIBUR_BASE + 0x0000)

#define EXCALIBUR_BOOT_CR_BM   0x00000001
#define EXCALIBUR_BOOT_CR_HM   0x00000002
#define EXCALIBUR_BOOT_CR_RE   0x00000004

//-----------------------------------------------------------------------------
// DPSRAM config
#define EXCALIBUR_DPSRAM_BASE  (EXCALIBUR_BASE + 0x0030)
#define _DPSRAM0_SR            0x0000
#define _DPSRAM0_LCR           0x0004
#define _DPSRAM1_SR            0x0008
#define _DPSRAM1_LCR           0x000c

#define _DPSRAM0_LCR_INIT      0x00000000
#define _DPSRAM1_LCR_INIT      0x00000000

//-----------------------------------------------------------------------------
// IO controller
#define EXCALIBUR_IOCR_BASE    (EXCALIBUR_BASE + 0x0040)
#define _IOCR_SDRAM            0x0000
#define _IOCR_EBI              0x0004
#define _IOCR_UART             0x0008
#define _IOCR_TRACE            0x000c

#define _IOCR_OC_PCI           0x00000008
#define _IOCR_OC_FAST          0x00000004
#define _IOCR_OC_SLOW          0x00000000
#define _IOCR_IO_STRIPE        0x00000002
#define _IOCR_LOCK             0x00000001

#define EXCALIBUR_IOCR_SDRAM_INIT (_IOCR_OC_FAST | _IOCR_IO_STRIPE | _IOCR_LOCK)
#define EXCALIBUR_IOCR_EBI_INIT   (_IOCR_OC_SLOW | _IOCR_IO_STRIPE | _IOCR_LOCK)
#define EXCALIBUR_IOCR_UART_INIT  (_IOCR_OC_SLOW | _IOCR_IO_STRIPE | _IOCR_LOCK)


//-----------------------------------------------------------------------------
// Memory mapping
#define EXCALIBUR_MMAP_BASE    (EXCALIBUR_BASE + 0x0080)
#define _MMAP_REGISTERS        0x0000
#define _MMAP_SRAM0            0x0010
#define _MMAP_SRAM1            0x0014
#define _MMAP_DPSRAM0          0x0020
#define _MMAP_DPSRAM1          0x0024
#define _MMAP_SDRAM0           0x0030
#define _MMAP_SDRAM1           0x0034
#define _MMAP_EBI0             0x0040
#define _MMAP_EBI1             0x0044
#define _MMAP_EBI2             0x0048
#define _MMAP_EBI3             0x004c
#define _MMAP_PLD0             0x0050
#define _MMAP_PLD1             0x0054
#define _MMAP_PLD2             0x0058
#define _MMAP_PLD3             0x005c

#define _MMAP_SIZE_16K   (13<<7)
#define _MMAP_SIZE_64K   (15<<7)
#define _MMAP_SIZE_128K  (16<<7)
#define _MMAP_SIZE_1M    (19<<7)
#define _MMAP_SIZE_4M    (21<<7)
#define _MMAP_SIZE_16M   (23<<7)
#define _MMAP_SIZE_32M   (24<<7)
#define _MMAP_SIZE_64M   (25<<7)

#define _MMAP_PREFETCH         0x00000000
#define _MMAP_NOPREFETCH       0x00000002

#define _MMAP_ENABLE           0x00000001
#define _MMAP_DISABLE          0x00000000

#define _MMAP_REGISTERS_INIT   (EXCALIBUR_REGS_PHYS_BASE  + 0x00000000 | _MMAP_SIZE_16K  | _MMAP_NOPREFETCH | _MMAP_ENABLE)
#define _MMAP_SRAM0_INIT       (EXCALIBUR_SRAM_PHYS_BASE  + 0x00000000 | _MMAP_SIZE_128K | _MMAP_PREFETCH   | _MMAP_ENABLE)
#define _MMAP_SRAM1_INIT       (EXCALIBUR_SRAM_PHYS_BASE  + 0x00020000 | _MMAP_SIZE_128K | _MMAP_PREFETCH   | _MMAP_ENABLE)
#define _MMAP_DPSRAM0_INIT     (EXCALIBUR_SRAM_PHYS_BASE  + 0x00040000 | _MMAP_SIZE_64K  | _MMAP_PREFETCH   | _MMAP_ENABLE)
#define _MMAP_DPSRAM1_INIT     (EXCALIBUR_SRAM_PHYS_BASE  + 0x00050000 | _MMAP_SIZE_64K  | _MMAP_PREFETCH   | _MMAP_ENABLE)
#define _MMAP_SDRAM0_INIT      (EXCALIBUR_SDRAM_PHYS_BASE + 0x00000000 | _MMAP_SIZE_64M  | _MMAP_PREFETCH   | _MMAP_ENABLE)
#define _MMAP_SDRAM1_INIT      (EXCALIBUR_SDRAM_PHYS_BASE + 0x04000000 | _MMAP_SIZE_64M  | _MMAP_PREFETCH   | _MMAP_ENABLE)
#define _MMAP_EBI0_INIT        (EXCALIBUR_FLASH_PHYS_BASE + 0x00000000 | _MMAP_SIZE_4M   | _MMAP_PREFETCH   | _MMAP_ENABLE)
#define _MMAP_EBI1_INIT        (EXCALIBUR_FLASH_PHYS_BASE + 0x00400000 | _MMAP_SIZE_4M   | _MMAP_PREFETCH   | _MMAP_ENABLE)
#define _MMAP_EBI2_INIT        (EXCALIBUR_FLASH_PHYS_BASE + 0x00800000 | _MMAP_SIZE_4M   | _MMAP_PREFETCH   | _MMAP_ENABLE)
#define _MMAP_EBI3_INIT        (EXCALIBUR_FLASH_PHYS_BASE + 0x00c00000 | _MMAP_SIZE_4M   | _MMAP_PREFETCH   | _MMAP_ENABLE)
#define _MMAP_PLD0_INIT        (EXCALIBUR_PLD_PHYS_BASE   + 0x00000000 | _MMAP_SIZE_16K | _MMAP_NOPREFETCH | _MMAP_ENABLE)
//#define _MMAP_PLD1_INIT        (EXCALIBUR_PLD_PHYS_BASE   + 0x00004000 | _MMAP_SIZE_16K | _MMAP_NOPREFETCH | _MMAP_ENABLE)
#define _MMAP_PLD1_INIT        (0x0f000000 | _MMAP_SIZE_16K | _MMAP_NOPREFETCH | _MMAP_ENABLE)
#define _MMAP_PLD2_INIT        (EXCALIBUR_PLD_PHYS_BASE   + 0x00008000 | _MMAP_SIZE_16K | _MMAP_NOPREFETCH | _MMAP_ENABLE)
#define _MMAP_PLD3_INIT        (EXCALIBUR_PLD_PHYS_BASE   + 0x0000c000 | _MMAP_SIZE_16K | _MMAP_NOPREFETCH | _MMAP_ENABLE)

#define EXCALIBUR_SDRAM_PHYS_BASE 0x00000000
#define EXCALIBUR_FLASH_PHYS_BASE 0x40000000
#define EXCALIBUR_SRAM_PHYS_BASE  0x08000000
#define EXCALIBUR_PLD_PHYS_BASE   0x80000000
#define EXCALIBUR_REGS_PHYS_BASE  0x7fffc000




//-----------------------------------------------------------------------------
// Timers
#define EXCALIBUR_TIMER0_CR              (EXCALIBUR_BASE+0x0200)
#define EXCALIBUR_TIMER0_PRE             (EXCALIBUR_BASE+0x0210)
#define EXCALIBUR_TIMER0_LIMIT           (EXCALIBUR_BASE+0x0220)
#define EXCALIBUR_TIMER0_READ            (EXCALIBUR_BASE+0x0230)

#define EXCALIBUR_TIMER1_CR              (EXCALIBUR_BASE+0x0240)
#define EXCALIBUR_TIMER1_PRE             (EXCALIBUR_BASE+0x0250)
#define EXCALIBUR_TIMER1_LIMIT           (EXCALIBUR_BASE+0x0260)
#define EXCALIBUR_TIMER1_READ            (EXCALIBUR_BASE+0x0270)

#define EXCALIBUR_TIMER_CR_MODE_HEARBEAT 0x00000000
#define EXCALIBUR_TIMER_CR_MODE_ONE_SHOT 0x00000001
#define EXCALIBUR_TIMER_CR_IE            0x00000004
#define EXCALIBUR_TIMER_CR_CI            0x00000008
#define EXCALIBUR_TIMER_CR_S             0x00000010

//-----------------------------------------------------------------------------
// Serial
#define EXCALIBUR_UART0_BASE            (EXCALIBUR_BASE+0x0280)
#define _UART_RSR              0x0000
#define _UART_RDS              0x0004
#define _UART_RD               0x0008
#define _UART_TSR              0x000c
#define _UART_TD               0x0010
#define _UART_FCR              0x0014
#define _UART_IES              0x0018
#define _UART_IEC              0x001c
#define _UART_ISR              0x0020