hal_platform_setup.h

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#ifndef CYGONCE_HAL_PLATFORM_SETUP_H
#define CYGONCE_HAL_PLATFORM_SETUP_H
//=============================================================================
//
//      hal_platform_setup.h
//
//      Platform specific support for HAL (assembly code)
//
//=============================================================================
//####ECOSGPLCOPYRIGHTBEGIN####
// -------------------------------------------
// This file is part of eCos, the Embedded Configurable Operating System.
// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
//
// eCos is free software; you can redistribute it and/or modify it under
// the terms of the GNU General Public License as published by the Free
// Software Foundation; either version 2 or (at your option) any later version.
//
// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or
// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
// for more details.
//
// You should have received a copy of the GNU General Public License along
// with eCos; if not, write to the Free Software Foundation, Inc.,
// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
//
// As a special exception, if other files instantiate templates or use macros
// or inline functions from this file, or you compile this file and link it
// with other works to produce a work based on this file, this file does not
// by itself cause the resulting work to be covered by the GNU General Public
// License. However the source code for this file must still be made available
// in accordance with section (3) of the GNU General Public License.
//
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// this file might be covered by the GNU General Public License.
//
// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
// at http://sources.redhat.com/ecos/ecos-license/
// -------------------------------------------
//####ECOSGPLCOPYRIGHTEND####
//=============================================================================
//#####DESCRIPTIONBEGIN####
//
// Author(s):    jskov
// Contributors: jskov, gthomas
// Date:         2001-08-06
// Purpose:      ARM9/EXCALIBUR platform specific support routines
// Description: 
// Usage:        #include <cyg/hal/hal_platform_setup.h>
//     Only used by "vectors.S"         
//
//####DESCRIPTIONEND####
//
//=============================================================================

#include <pkgconf/system.h>             // System-wide configuration info
#include CYGBLD_HAL_VARIANT_H           // Variant specific configuration
#include CYGBLD_HAL_PLATFORM_H          // Platform specific configuration
#include CYGHWR_MEMORY_LAYOUT_H
#include <cyg/hal/hal_mmu.h>            // MMU definitions
#include <cyg/hal/excalibur.h>          // Platform specific hardware definitions

#define nDEBUG
#define n_ALTERA_CACHEHACK  // doesn't have any apparent effect

#if defined(CYG_HAL_STARTUP_ROM) || defined(CYG_HAL_STARTUP_ROMRAM) || defined(CYG_HAL_STARTUP_REDBOOT)
#define PLATFORM_SETUP1 _platform_setup1
#define CYGHWR_HAL_ARM_HAS_MMU
#define CYGSEM_HAL_ROM_RESET_USES_JUMP

#define CYG_DEVICE_SERIAL_BAUD_DIV (CYGNUM_HAL_ARM_EXCALIBUR_PERIPHERAL_CLOCK/CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_BAUD/16)
#define CYG_DEVICE_SERIAL_BAUD_LSB (CYG_DEVICE_SERIAL_BAUD_DIV&0xff)
#define CYG_DEVICE_SERIAL_BAUD_MSB ((CYG_DEVICE_SERIAL_BAUD_DIV>>8)&0xff)

// We need this here - can't rely on a translation table until MMU has
// been initialized
        .macro RAW_LED_MACRO x
#ifdef DEBUG
        ldr     r0,=(EXCALIBUR_UART0_BASE+_UART_TD)
        mov     r1,#(\x + 0x41)
        str     r1,[r0]
#endif
        .endm

// This macro represents the initial startup code for the platform        
        .macro  _platform_setup1
        // IO controller init
        ldr     r1,=EXCALIBUR_IOCR_BASE
        ldr     r2,=EXCALIBUR_IOCR_SDRAM_INIT
        str     r2,[r1,#_IOCR_SDRAM]
        ldr     r2,=EXCALIBUR_IOCR_EBI_INIT
        str     r2,[r1,#_IOCR_EBI]
        ldr     r2,=EXCALIBUR_IOCR_UART_INIT
        str     r2,[r1,#_IOCR_UART]

        // Expansion bus init
        ldr     r1,=EXCALIBUR_EBI_CR
        ldr     r2,=EXCALIBUR_EBI_CR_INIT
        str     r2,[r1]

#ifdef DEBUG
        // Init UART for debug tracing
        ldr     r4,=EXCALIBUR_UART0_BASE
        ldr     r2,=(_UART_MC_8BIT | _UART_MC_1STOP | _UART_MC_PARITY_NONE)
        str     r2,[r4,#_UART_MC]
        ldr     r2,=CYG_DEVICE_SERIAL_BAUD_LSB
        str     r2,[r4,#_UART_DIV_LO]
        ldr     r2,=CYG_DEVICE_SERIAL_BAUD_MSB
        str     r2,[r4,#_UART_DIV_HI]
        ldr     r2,=(_UART_FCR_TC | _UART_FCR_RC | _UART_FCR_TX_THR_15 | _UART_FCR_RX_THR_1)
        str     r2,[r4,#_UART_FCR]
#endif

        // Setup the PLLs see the label PLL_ADDR below for the input
        // clock frequency and the desired output frequencies of PLL1
        // and PLL2 Load the value into K,M,N for PLL 1 and 2
        adr     r0,2f
        ldmia   r0,{r0-r11}
        str     r6,[r0]
        str     r7,[r1]
        str     r8,[r2]
        str     r9,[r3]
        str     r10,[r4]
        str     r11,[r5]
                
        // Turn on the PLLs
        ldr     r3,=EXCALIBUR_CLK_BASE
        ldr     r1,=(0x1035 | _CLK_PLL1_CTRL_P)
        str     r1,[r3, #_CLK_PLL1_CTRL]
        str     r1,[r3, #_CLK_PLL2_CTRL]

        // Ensure the PLLs are not in bypass
        ldr     r1,=(0x10 | _CLK_DERIVE_BP1 | _CLK_DERIVE_BP2)
        str     r1,[r3, #_CLK_DERIVE]
        orr     r1,r1,#0x300 /* Use PLL2 for AHB and for the SDRAM */
        str     r1,[r3, #_CLK_DERIVE]
        ldr     r2,=(_CLK_DERIVE_BP1 | _CLK_DERIVE_BP2)
        bic     r1,r1,r2
        str     r1,[r3, #_CLK_DERIVE]

        // Poll waiting for the PLL's to lock and the bits to not be
        // in bypass mode
        ldr     r2,=_CLK_STATUS_L2 /*_CLK_STATUS_L1 | _CLK_STATUS_L2*/
1:      ldr     r1, [r3, #_CLK_STATUS]
        and     r1, r1, r2
        cmp     r1, r2
        bne     1b

        // Clear the interrupt caused by the change in lock status
        ldr     r2, =(_CLK_STATUS_C1 | _CLK_STATUS_C2)
        str     r2, [r3, #_CLK_STATUS]
        
        b       3f

        // PLL Registers Addresses
2:      .long EXCALIBUR_CLK_BASE+_CLK_PLL1_KCNT
        .long EXCALIBUR_CLK_BASE+_CLK_PLL1_MCNT
        .long EXCALIBUR_CLK_BASE+_CLK_PLL1_NCNT
        .long EXCALIBUR_CLK_BASE+_CLK_PLL2_KCNT
        .long EXCALIBUR_CLK_BASE+_CLK_PLL2_MCNT
        .long EXCALIBUR_CLK_BASE+_CLK_PLL2_NCNT
        // PLL Registers Values ensure this follows on from the
        // addresses the code depends on it
        .long 0x40000 // CLK_PLL1_KCNT_VAL  = 1
        .long 0x20101 // CLK_PLL1_MCNT_VAL  = 2
        .long 0x40000 // CLK_PLL1_NCNT_VAL  = 1
        .long 0x40000 // CLK_PLL2_KCNT_VAL  = 1
        .long 0x20303 // CLK_PLL2_MCNT_VAL  = 6
        .long 0x40000 // CLK_PLL2_NCNT_VAL  = 1
3:

        RAW_LED_MACRO 0

        // Jump to ROM
        ldr     r1,=(EXCALIBUR_MMAP_BASE + _MMAP_EBI0)
        ldr     r2,=_MMAP_EBI0_INIT
        str     r2,[r1]
        ldr     r1,=CYGMEM_REGION_rom
        add     pc,pc,r1
        nop
        nop

        // Disable ROM mapping
        ldr     r1,=EXCALIBUR_BOOT_CR
        ldr     r2,=EXCALIBUR_BOOT_CR_BM
        str     r2,[r1]

        RAW_LED_MACRO 1

        // Disable and clear caches
        
        mrc  p15,0,r0,c1,c0,0
        bic  r0,r0,#0x1000              // disable ICache
        bic  r0,r0,#0x0007              // disable DCache,
                                        // MMU and alignment faults
        mcr  p15,0,r0,c1,c0,0
        nop
        nop
        nop
        nop
        nop
        nop
        nop
        nop
        mov  r0,#0
        mcr  p15,0,r0,c7,c6,0           // clear data cache
        mcr  p15,0,r0,c7,c5,0           // clear instruction cache
        
#if 0
        mrc  p15,0,r0,c15,c1,0          // disable streaming
        orr  r0,r0,#0x80
        mcr  p15,0,r0,c15,c1,0
#endif

        RAW_LED_MACRO 2

        // Set memory mapping
        ldr     r1,=EXCALIBUR_MMAP_BASE
        ldr     r2,=_MMAP_REGISTERS_INIT
        str     r2,[r1,#_MMAP_REGISTERS]
        ldr     r2,=_MMAP_SRAM0_INIT
        str     r2,[r1,#_MMAP_SRAM0]
        ldr     r2,=_MMAP_SRAM1_INIT
        str     r2,[r1,#_MMAP_SRAM1]
        ldr     r2,=_MMAP_DPSRAM0_INIT
        str     r2,[r1,#_MMAP_DPSRAM0]
        ldr     r2,=_MMAP_DPSRAM1_INIT
        str     r2,[r1,#_MMAP_DPSRAM1]
        ldr     r2,=_MMAP_SDRAM0_INIT
        str     r2,[r1,#_MMAP_SDRAM0]
        ldr     r2,=_MMAP_SDRAM1_INIT
        str     r2,[r1,#_MMAP_SDRAM1]
        ldr     r2,=_MMAP_PLD0_INIT
        str     r2,[r1,#_MMAP_PLD0]
        ldr     r2,=_MMAP_PLD1_INIT
        str     r2,[r1,#_MMAP_PLD1]
        ldr     r2,=_MMAP_PLD2_INIT
        str     r2,[r1,#_MMAP_PLD2]
        ldr     r2,=_MMAP_PLD3_INIT
        str     r2,[r1,#_MMAP_PLD3]
        ldr     r2,=_MMAP_EBI1_INIT
        str     r2,[r1,#_MMAP_EBI1]
        ldr     r2,=_MMAP_EBI2_INIT
        str     r2,[r1,#_MMAP_EBI2]
        ldr     r2,=_MMAP_EBI3_INIT
        str     r2,[r1,#_MMAP_EBI3]

        RAW_LED_MACRO 3

        // FIXME: Disable MMAP registers?

        RAW_LED_MACRO 4