aaed2000_misc.c

eCos操作系统源码

}

// -------------------------------------------------------------------------
void hal_clock_initialize(cyg_uint32 period)
{
    // Use timer1 for the kernel clock
    HAL_WRITE_UINT32(AAEC_TMR_T1LOAD, period);
    HAL_WRITE_UINT32(AAEC_TMR_T1CONTROL, 
                     AAEC_TMR_TxCONTROL_ENABLE
                     | AAEC_TMR_TxCONTROL_MODE_PERIODIC
                     | AAEC_TMR_TxCONTROL_508KHZ);

    // Unmask timer 0 interrupt
    HAL_INTERRUPT_CONFIGURE( CYGNUM_HAL_INTERRUPT_RTC, 1, 1 );
    HAL_INTERRUPT_UNMASK( CYGNUM_HAL_INTERRUPT_RTC );
}

// This routine is called during a clock interrupt.
void hal_clock_reset(cyg_uint32 vector, cyg_uint32 period)
{
    // Clear pending interrupt bit
    HAL_INTERRUPT_ACKNOWLEDGE(vector);
}

// Read the current value of the clock, returning the number of hardware
// "ticks" that have occurred (i.e. how far away the current value is from
// the start)

// Note: The "contract" for this function is that the value is the number
// of hardware clocks that have happened since the last interrupt (i.e.
// when it was reset).

void hal_clock_read(cyg_uint32 *pvalue)
{
    cyg_uint32 ctr;

    HAL_READ_UINT32(AAEC_TMR_T1VALUE, ctr);
    ctr = CYGNUM_HAL_RTC_PERIOD - ctr;
    *pvalue = ctr;
}

//
// Delay for some number of micro-seconds
//   Use timer #3 which runs at [fixed] 7.3728 MHz
//   Since this is only a 16 bit counter, it may be necessary
//   to run a loop to achieve sufficiently large delay values.
//
// Note: The 7.3728MHz value does not seem to work in practice
// It seems to be off by about a factor of 2.
//
void hal_delay_us(cyg_int32 usecs)
{
    static struct _tmr_vals {
        int us_val, tmr_val;
    } tmr_vals[] = {
        { 2*1000, 7372 },
        {  2*100,  737 },
        {   2*10,   74 },
        {    2*1,    7 },
        {      0,    0 }
    };
    struct _tmr_vals *vals = tmr_vals;
    cyg_uint32 state;
    
    while (vals->tmr_val) {
        while (usecs >= vals->us_val) {
            // disable timer #3
            HAL_WRITE_UINT32(AAEC_TMR_T3CONTROL, 0);
            HAL_WRITE_UINT32(AAEC_TMR_T3EOI, 0);
            // configure for tmr_val
            HAL_WRITE_UINT32(AAEC_TMR_T3LOAD, vals->tmr_val);
            // enable
            HAL_WRITE_UINT32(AAEC_TMR_T3CONTROL, 
                             AAEC_TMR_TxCONTROL_ENABLE | AAEC_TMR_TxCONTROL_MODE_FREE);
            // wait for overflow
            do {
                HAL_READ_UINT32(AAEC_INT_RSR, state);
            } while ((state & (1<<AAEC_INTS_T3OI)) == 0);
            usecs -= vals->us_val;
        }
        vals++;
    }
}

// -------------------------------------------------------------------------

// This routine is called to respond to a hardware interrupt (IRQ).  It
// should interrogate the hardware and return the IRQ vector number.
int hal_IRQ_handler(void)
{
    int irq = CYGNUM_HAL_INTERRUPT_NONE;
    int vec;
    cyg_uint32 sr;

    HAL_READ_UINT32(AAEC_INT_SR, sr);
    for (vec = 0; vec <= CYGNUM_HAL_INTERRUPT_BMIINTR; vec++) {
        if (sr & (1<<vec)) {
            irq = vec;
            break;
        }
    }

    return irq;
}

//
// Interrupt control
//

struct {
    int   gpio_int;   // GPIO (F) interrupt source
    cyg_haladdress eoi;        // Acknowledge location
} AAED2000_INTMAP[] = {
    { 0, 0}, // CYGNUM_HAL_INTERRUPT_TS            CYGNUM_HAL_INTERRUPT_GPIO0FIQ
    {-1, AAEC_CSC_BLEOI}, // CYGNUM_HAL_INTERRUPT_BLINT         1
    {-1, AAEC_CSC_TEOI},  // CYGNUM_HAL_INTERRUPT_WEINT         2
    {-1, AAEC_CSC_MCEOI}, // CYGNUM_HAL_INTERRUPT_MCINT         3
    {-1, AAEC_COD_CDEOI}, // CYGNUM_HAL_INTERRUPT_CSINT         4
    { 1, 0}, // CYGNUM_HAL_INTERRUPT_ETH           CYGNUM_HAL_INTERRUPT_GPIO1INTR
    { 2, 0}, // CYGNUM_HAL_INTERRUPT_PCMCIA_CD2    CYGNUM_HAL_INTERRUPT_GPIO2INTR
    { 3, 0}, // CYGNUM_HAL_INTERRUPT_PCMCIA_CD1    CYGNUM_HAL_INTERRUPT_GPIO3INTR
    {-1, AAEC_TMR_T1EOI}, // CYGNUM_HAL_INTERRUPT_TC1OI         8
    {-1, AAEC_TMR_T2EOI}, // CYGNUM_HAL_INTERRUPT_TC2OI         9
    {-1, AAEC_RTC_RTCEOI},// CYGNUM_HAL_INTERRUPT_RTCMI        10
    {-1, AAEC_CSC_TEOI},  // CYGNUM_HAL_INTERRUPT_TINTR        11
    {-1, 0}, // CYGNUM_HAL_INTERRUPT_UART1INTR    12
    {-1, AAEC_UART2_UMS2EOI}, // CYGNUM_HAL_INTERRUPT_UART2INTR    13
    {-1, 0}, // CYGNUM_HAL_INTERRUPT_LCDINTR      14
    {-1, 0}, // CYGNUM_HAL_INTERRUPT_SSEOTI       15
    {-1, AAEC_UART2_UMS3EOI}, // CYGNUM_HAL_INTERRUPT_UART3INTR    16
    {-1, 0}, // CYGNUM_HAL_INTERRUPT_SCIINTR      17
    {-1, 0}, // CYGNUM_HAL_INTERRUPT_AACINTR      18
    {-1, 0}, // CYGNUM_HAL_INTERRUPT_MMCINTR      19
    {-1, 0}, // CYGNUM_HAL_INTERRUPT_USBINTR      20
    {-1, 0}, // CYGNUM_HAL_INTERRUPT_DMAINTR      21
    {-1, AAEC_TMR_T3EOI}, // CYGNUM_HAL_INTERRUPT_TC3OI        22
    { 4, 0}, // CYGNUM_HAL_INTERRUPT_SCI_VCCEN    CYGNUM_HAL_INTERRUPT_GPIO4INTR
    { 5, 0}, // CYGNUM_HAL_INTERRUPT_SCI_DETECT   CYGNUM_HAL_INTERRUPT_GPIO5INTR
    { 6, 0}, // CYGNUM_HAL_INTERRUPT_PCMCIA_RDY1  CYGNUM_HAL_INTERRUPT_GPIO6INTR
    { 7, 0}, // CYGNUM_HAL_INTERRUPT_PCMCIA_RDY2  CYGNUM_HAL_INTERRUPT_GPIO7INTR
    {-1, 0}, // CYGNUM_HAL_INTERRUPT_BMIINTR      27
};

void hal_interrupt_mask(int vector)
{
    CYG_ASSERT(vector <= CYGNUM_HAL_ISR_MAX &&
               vector >= CYGNUM_HAL_ISR_MIN , "Invalid vector");

    if (vector <= CYGNUM_HAL_INTERRUPT_BMIINTR) {
        HAL_WRITE_UINT32(AAEC_INT_ENC, (1 << vector));
    }
}

void hal_interrupt_unmask(int vector)
{
    CYG_ASSERT(vector <= CYGNUM_HAL_ISR_MAX &&
               vector >= CYGNUM_HAL_ISR_MIN , "Invalid vector");

    if (vector <= CYGNUM_HAL_INTERRUPT_BMIINTR) {
        HAL_WRITE_UINT32(AAEC_INT_ENS, (1 << vector));
    }
}

void hal_interrupt_acknowledge(int vector)
{
    cyg_haladdress eoi;
    int gpio;
    CYG_ASSERT(vector <= CYGNUM_HAL_ISR_MAX &&
               vector >= CYGNUM_HAL_ISR_MIN , "Invalid vector");

    if (vector <= CYGNUM_HAL_INTERRUPT_BMIINTR) {
        // Must be cleared at the source
        if ((eoi = AAED2000_INTMAP[vector].eoi) != 0) {
            HAL_WRITE_UINT32(eoi, 0);  // Any write clears interrupt
        } else if ((gpio = AAED2000_INTMAP[vector].gpio_int) >= 0) {
            // GPIO interrupts require special care
            HAL_WRITE_UINT32(AAEC_GPIO_FEOI, (1<<gpio));
        }
    }
}

void hal_interrupt_configure(int vector, int level, int up)
{
    int gpio;
    CYG_ASSERT(vector <= CYGNUM_HAL_ISR_MAX &&
               vector >= CYGNUM_HAL_ISR_MIN , "Invalid vector");
    if (vector <= CYGNUM_HAL_INTERRUPT_BMIINTR) {
        if ((gpio = AAED2000_INTMAP[vector].gpio_int) >= 0) {
            // Only GPIO interrupts can be configured
            int mask = (1<<gpio);
            cyg_uint32 cur;
            // Set type (level or edge)
            HAL_READ_UINT32(AAEC_GPIO_INT_TYPE1, cur);
            if (level) {
                // Level driven
                cur &= ~mask;
            } else {
                // Edge driven
                cur |= mask;
            }
            HAL_WRITE_UINT32(AAEC_GPIO_INT_TYPE1, cur);
            // Set level (high/rising or low/falling)
            HAL_READ_UINT32(AAEC_GPIO_INT_TYPE2, cur);
            if (up) {
                // Trigger on high/rising
                cur |= mask;
            } else {
                // Trigger on low/falling
                cur &= ~mask;
            }
            HAL_WRITE_UINT32(AAEC_GPIO_INT_TYPE2, cur);
            // Enable as interrupt
            HAL_READ_UINT32(AAEC_GPIO_INTEN, cur);
            cur |= mask;
            HAL_WRITE_UINT32(AAEC_GPIO_INTEN, cur);
        }
    }
}

void hal_interrupt_set_level(int vector, int level)
{
}

cyg_uint32
hal_virt_to_phys_address(cyg_uint32 virt)
{
    cyg_uint32 phys = 0xFFFFFFFF, dram_page;
    static cyg_uint32 _dram_map[] = {
        0xF0000000, 0xF1000000, 0xF4000000, 0xF5000000,
        0xF8000000, 0xF9000000, 0xFC000000, 0xFD000000
    };

    // Hard-wired, rather than walk the tables
    switch ((virt & 0xF0000000) >> 28) {
    case 0x0: // DRAM
        if ((virt & 0x0E000000) == 0) {
            dram_page = _dram_map[((virt & 0x01C00000) >> 22)];
            phys = dram_page | virt;
        } else {
            phys = 0xFFFFFFFF;
        }
        break;
    case 0x6: // FLASH
        phys = (virt & 0x0FFFFFFF);
        break;
    case 0x1:
    case 0x2:
    case 0x7:
    case 0x9:
    case 0xA:
    case 0xB:
    case 0xC:
    case 0xD:
    case 0xE:
        // Not mapped
        phys = 0xFFFFFFFF;
        break;
    case 0x3:
    case 0x4:
    case 0x5:
    case 0x8:
    case 0xF:
        // Mapped 1-1
        phys = virt;
        break;
    }
    return phys;
}