hal_platform_setup.h
来自「eCos操作系统源码」· C头文件 代码 · 共 983 行 · 第 1/2 页
H
983 行
ldr r0, REG_PULL_DWN_CTRL_3 ldr r1, VAL_PULL_DWN_CTRL_3 str r1, [r0] ldr r0, REG_FUNC_MUX_CTRL_4 ldr r1, VAL_FUNC_MUX_CTRL_4 str r1, [r0] ldr r0, REG_FUNC_MUX_CTRL_5 ldr r1, VAL_FUNC_MUX_CTRL_5 str r1, [r0] ldr r0, REG_FUNC_MUX_CTRL_6 ldr r1, VAL_FUNC_MUX_CTRL_6 str r1, [r0] ldr r0, REG_FUNC_MUX_CTRL_7 ldr r1, VAL_FUNC_MUX_CTRL_7 str r1, [r0] ldr r0, REG_FUNC_MUX_CTRL_8 ldr r1, VAL_FUNC_MUX_CTRL_8 str r1, [r0] ldr r0, REG_FUNC_MUX_CTRL_9 ldr r1, VAL_FUNC_MUX_CTRL_9 str r1, [r0] ldr r0, REG_FUNC_MUX_CTRL_A ldr r1, VAL_FUNC_MUX_CTRL_A str r1, [r0] ldr r0, REG_FUNC_MUX_CTRL_B ldr r1, VAL_FUNC_MUX_CTRL_B str r1, [r0] ldr r0, REG_FUNC_MUX_CTRL_C ldr r1, VAL_FUNC_MUX_CTRL_C str r1, [r0] ldr r0, REG_FUNC_MUX_CTRL_D ldr r1, VAL_FUNC_MUX_CTRL_D str r1, [r0] ldr r0, REG_VOLTAGE_CTRL_0 ldr r1, VAL_VOLTAGE_CTRL_0 str r1, [r0] ldr r0, REG_TEST_DBG_CTRL_0 ldr r1, VAL_TEST_DBG_CTRL_0 str r1, [r0] ldr r0, REG_MOD_CONF_CTRL_0 ldr r1, VAL_MOD_CONF_CTRL_0 str r1, [r0] FAKE_LED_MACRO(13) // Take out of compatibility mode ldr r0, REG_COMP_MODE_CTRL_0 ldr r1, VAL_COMP_MODE_CTRL_0 str r1, [r0] FAKE_LED_MACRO(14) b post_config_registers omap1509: ldr r0, REG_FUNC_MUX_CTRL_0 ldr r1, [r0] orr r1, r1, #0x6000000 // UART_GIGA_GATE bit as well as UART_BT_GATE bit str r1, [r0]// Errata for ES5.5 says this must be done before DSP or MPU can// access internal RAMs. This is benign for earlier revs. ldr r0, REG_FUNC_MUX_CTRL_1 mov r1, #0xc str r1, [r0] post_config_registers: FAKE_LED_MACRO(15) mov r0, #0x1800again: subs r0, r0, #0x1 bne again FAKE_LED_MACRO(16)// Invalidate cache// ----------------- mov r0,#0 nop mcr p15, 0x0, r0, c7, c5, 0x0 nop nop nop nop FAKE_LED_MACRO(17)// Enable I-Cache// ------------- mrc p15, 0x0, r1, c1, c0, 0x0 orr r1, r1, #0x1000 nop mcr p15, 0x0, r1, c1, c0, 0x0 nop nop nop nop FAKE_LED_MACRO(18)// Initialize Traffic Controller (TC)// ---------------------------------- ldr r0, REG_TC_IMIF_PRIO mov r1, #0x0 str r1, [r0] ldr r0, REG_TC_EMIFS_PRIO str r1, [r0] ldr r0, REG_TC_EMIFF_PRIO str r1, [r0] ldr r0, REG_TC_EMIFS_CONFIG ldr r1, [r0] bic r1, r1, #0x08 /* clear the global power-down enable PDE bit */ bic r1, r1, #0x01 /* write protect flash by clearing the WP bit */ str r1, [r0] // EMIFS GlB Configuration. (value 0x12 most likely)// Set TC chip select registers// SDRAM value based on 168MHz 1510.// ---------------------------- ldr r0, REG_TC_EMIFS_CS1_CONFIG ldr r1, VAL_TC_EMIFS_CS1_CONFIG_PRELIM str r1, [r0] ldr r0, REG_TC_EMIFS_CS2_CONFIG ldr r1, VAL_TC_EMIFS_CS2_CONFIG_PRELIM str r1, [r0] ldr r0, REG_TC_EMIFF_SDRAM_CONFIG ldr r1, VAL_TC_EMIFF_SDRAM_CONFIG str r1, [r0] ldr r0, REG_TC_EMIFF_MRS ldr r1, VAL_TC_EMIFF_MRS str r1, [r0] mov r0,#0x1800again2: subs r0,r0,#0x1 bne again2 FAKE_LED_MACRO(19) // Next, Enable the RS232 Line Drivers in the FPGA. // Also, power on the audio CODEC's amplifier here, // which will make a noise on the audio output. // This is done here instead of in the kernel so there // isn't a loud popping noise at the start of each // song. // Also, disable the CODEC's clocks. // omap1510-HelenP1 [specific] ldr r0, REG_FPGA_POWER mov r1, #0 ldr r2, REG_FPGA_DIP_SWITCH ldrb r3, [r2] cmp r3, #0x8 movne r1, #0x62 // Enable the RS232 Line Drivers in the EPLD strb r1, [r0] ldr r0, REG_FPGA_AUDIO mov r1, #0x0 // Disable sound driver (CODEC clocks) strb r1, [r0] mov r0, #0x1800again0: subs r0, r0, #0x1 bne again0 FAKE_LED_MACRO(20)// Init RHEA// ---------- ldr r1, V_0x0000ff22 mov r0, #0x0 str r1, [r0] // yep, that's really a write to address 0x00000000.// *revisit-skranz* is needed? mov r0, #0x1800again12: subs r0, r0, #0x1 bne again12 FAKE_LED_MACRO(21) // Misc 2// ------ mov r1, #0xfb ldr r0, REG_LB_CLOCK_DIV str r1, [r0]// *revisit-skranz* is needed? mov r0, #0x1800again4: subs r0, r0, #0x1 bne again4 FAKE_LED_MACRO(22)// ARM Clock Module Setup// ---------------------- mov r1, #0x40 ldr r0, REG_ARM_IDLECT2 strh r1, [r0] // CLKM, Clock domain control. mov r1, #0x01 // PER_EN bit ldr r0, REG_ARM_RSTCT2 strh r1, [r0] // CLKM; Peripheral reset. // Reset CLKM#ifdef ORIGINAL_CODE mov r1, #0x06 // Needed for UART[12]#else mov r1, #0x86 // Needed for UART[12]#endif ldr r0, REG_ARM_IDLECT2 strh r1, [r0] // CLKM, Clock domain control. // Set CLKM to Sync-Scalable mov r1, #0x1000 // Needed for UART[12] ldr r0, REG_ARM_SYSST strh r1, [r0] // *revisit-skranz* is needed? mov r0, #0x1800again6: subs r0, r0, #0x1 bne again6 FAKE_LED_MACRO(23) ldr r1, VAL_ARM_CKCTL ldr r0, REG_ARM_CKCTL strh r1, [r0] // setup DPLL1 Control Register// ---------------------------- ldr r1, VAL_DPLL1_CTL ldr r0, REG_DPLL1_CTL strh r1, [r0] ands r1, r1, #0x10 // Check if PLL is enabled. beq finish2 // Do not look for lock if BYPASS selectedpoll2: ldrh r1, [r0] ands r1, r1, #0x01 // Check the LOCK bit. beq poll2 // ...loop until bit goes hi.finish2: FAKE_LED_MACRO(24) // Setup TC EMIFS configuration. // CS0 value based on 168MHz // --------------------------------------------------- ldr r1, VAL_TC_EMIFS_CS0_CONFIG // increase flash speed. ldr r0, REG_TC_EMIFS_CS0_CONFIG str r1, [r0] // Chip Select 0 ldr r1, VAL_TC_EMIFS_CS1_CONFIG ldr r0, REG_TC_EMIFS_CS1_CONFIG str r1, [r0] // Chip Select 1 ldr r1, VAL_TC_EMIFS_CS2_CONFIG ldr r0, REG_TC_EMIFS_CS2_CONFIG str r1, [r0] // Chip Select 2 ldr r1, VAL_TC_EMIFS_CS3_CONFIG ldr r0, REG_TC_EMIFS_CS3_CONFIG str r1, [r0] // Chip Select 3 // *revisit-skranz* is needed? mov r0, #0x1800again9: subs r0, r0, #0x1 bne again9 FAKE_LED_MACRO(25) // The following was added by WPD // Set up a stack [for calling C code]#ifdef CYG_HAL_STARTUP_ROM // The startup stack is in internal SRAM ldr sp,=__startup_stack // This _MOST_DEFINATELY_ needs to be fixed orr sp,sp,#0x10000000#else // The startup stack is in SDRAM, at some virtual address, but // we have not set up the MMU yet, so we need to initialize SP // with the physical address of '__startup_stack'#error "Somehow"#endif bl hal_mmu_init FAKE_LED_MACRO(26) // Enable MMU ldr r2,=10f ldr r1,=MMU_Control_Init|MMU_Control_M mcr MMU_CP,0,r1,MMU_Control,c0 mov pc,r2 // mcr MMU_CP,0,r0,MMU_InvalidateCache,c7,0 // Flush data and instruction cache // mcr MMU_CP,0,r0,MMU_TLB,c7,0 // Flush ID TLBs10: nop nop nop FAKE_LED_MACRO(27)#if 0 ldr r3,=0x20000000 str r1,[r3] mrc MMU_CP,0,r1,MMU_Control,c0 str r1,[r3, #0x04] mrc p15,0,r1,c15,c1,0 str r1,[r3, #0x08]here: // b here#endif#endif .endm #else // defined(CYG_HAL_STARTUP_ROM) || defined(CYG_HAL_STARTUP_ROMRAM) || defined(CYG_HAL_STARTUP_REDBOOT)#define PLATFORM_SETUP1#endif//-----------------------------------------------------------------------------//-----------------------------------------------------------------------------// end of hal_platform_setup.h// ------------------------------------------------------ // --------------Static Data Definitions-----------------// ------------------------------------------------------/* inernal OMAP registers */ /* interrupt handler level 2 registers */REG_IHL2_MIR: /* 32 bits */ .word 0xfffe0004 /* OMAP configuration registers */REG_FUNC_MUX_CTRL_0: /* 32 bits */ .word 0xfffe1000REG_FUNC_MUX_CTRL_1: /* 32 bits */ .word 0xfffe1004REG_FUNC_MUX_CTRL_2: /* 32 bits */ .word 0xfffe1008REG_COMP_MODE_CTRL_0: /* 32 bits */ .word 0xfffe100cREG_FUNC_MUX_CTRL_3: /* 32 bits */ .word 0xfffe1010REG_FUNC_MUX_CTRL_4: /* 32 bits */ .word 0xfffe1014REG_FUNC_MUX_CTRL_5: /* 32 bits */ .word 0xfffe1018REG_FUNC_MUX_CTRL_6: /* 32 bits */ .word 0xfffe101cREG_FUNC_MUX_CTRL_7: /* 32 bits */ .word 0xfffe1020REG_FUNC_MUX_CTRL_8: /* 32 bits */ .word 0xfffe1024REG_FUNC_MUX_CTRL_9: /* 32 bits */ .word 0xfffe1028REG_FUNC_MUX_CTRL_A: /* 32 bits */ .word 0xfffe102CREG_FUNC_MUX_CTRL_B: /* 32 bits */ .word 0xfffe1030REG_FUNC_MUX_CTRL_C: /* 32 bits */ .word 0xfffe1034REG_FUNC_MUX_CTRL_D: /* 32 bits */ .word 0xfffe1038REG_PULL_DWN_CTRL_0: /* 32 bits */ .word 0xfffe1040REG_PULL_DWN_CTRL_1: /* 32 bits */ .word 0xfffe1044REG_PULL_DWN_CTRL_2: /* 32 bits */ .word 0xfffe1048REG_PULL_DWN_CTRL_3: /* 32 bits */ .word 0xfffe104cREG_VOLTAGE_CTRL_0: /* 32 bits */ .word 0xfffe1060REG_TEST_DBG_CTRL_0: /* 32 bits */ .word 0xfffe1070REG_MOD_CONF_CTRL_0: /* 32 bits */ .word 0xfffe1080 /* local bus control registers */REG_LB_CLOCK_DIV: /* 32 bits */ .word 0xfffec10c /* watchdog timer registers */REG_WDT_TIMER_MODE: /* 16 bits */ .word 0xfffec808 /* interrupt handler level 1 registers */REG_IHL1_MIR: /* 32 bits */ .word 0xfffecb04 /* traffic controller memory interface registers */REG_TC_IMIF_PRIO: /* 32 bits */ .word 0xfffecc00REG_TC_EMIFS_PRIO: /* 32 bits */ .word 0xfffecc04REG_TC_EMIFF_PRIO: /* 32 bits */ .word 0xfffecc08REG_TC_EMIFS_CONFIG: /* 32 bits */ .word 0xfffecc0cREG_TC_EMIFS_CS0_CONFIG: /* 32 bits */ .word 0xfffecc10REG_TC_EMIFS_CS1_CONFIG: /* 32 bits */ .word 0xfffecc14REG_TC_EMIFS_CS2_CONFIG: /* 32 bits */ .word 0xfffecc18REG_TC_EMIFS_CS3_CONFIG: /* 32 bits */ .word 0xfffecc1cREG_TC_EMIFF_SDRAM_CONFIG: /* 32 bits */ .word 0xfffecc20REG_TC_EMIFF_MRS: /* 32 bits */ .word 0xfffecc24 /* MPU clock/reset/power mode control registers */REG_ARM_CKCTL: /* 16 bits */ .word 0xfffece00REG_ARM_IDLECT2: /* 16 bits */ .word 0xfffece08REG_ARM_RSTCT2: /* 16 bits */ .word 0xfffece14REG_ARM_SYSST: /* 16 bits */ .word 0xfffece18 /* DPLL control registers */REG_DPLL1_CTL: /* 16 bits */ .word 0xfffecf00 /* identification code register */REG_IDCODE: /* 32 bits */ .word 0xfffed404 /* board-specific registers */REG_FPGA_LED_DIGIT: /* 8 bits (not used on Innovator) */ .word 0x08000003REG_FPGA_POWER: /* 8 bits */ .word 0x08000005REG_FPGA_AUDIO: /* 8 bits (not used on Innovator) */ .word 0x0800000cREG_FPGA_DIP_SWITCH: /* 8 bits (not used on Innovator) */ .word 0x0800000e/* constants */VAL_COMP_MODE_CTRL_0: .word 0x0000eaefVAL_FUNC_MUX_CTRL_4: .word 0x00000000VAL_FUNC_MUX_CTRL_5: .word 0x00000000VAL_FUNC_MUX_CTRL_6: .word 0x00000001VAL_FUNC_MUX_CTRL_7: .word 0x00000000VAL_FUNC_MUX_CTRL_8: .word 0x10001200VAL_FUNC_MUX_CTRL_9: .word 0x01201012VAL_FUNC_MUX_CTRL_A: .word 0x00000248VAL_FUNC_MUX_CTRL_B: .word 0x00000248VAL_FUNC_MUX_CTRL_C: .word 0x09000000VAL_FUNC_MUX_CTRL_D: .word 0x00000000VAL_PULL_DWN_CTRL_0: .word 0x11a10000VAL_PULL_DWN_CTRL_1: .word 0x2e047fffVAL_PULL_DWN_CTRL_2: .word 0xffd7d3e6VAL_PULL_DWN_CTRL_3: .word 0x00003f03VAL_VOLTAGE_CTRL_0: .word 0x00000007VAL_TEST_DBG_CTRL_0: /* The OMAP5910 TRM says this register must be 0, but HelenConfRegs * says to write a 7. Don't know what the right thing is to do, so * I'm leaving it at 7 since that's what was already here. */ .word 0x00000007VAL_MOD_CONF_CTRL_0: .word 0x0b000008VAL_ARM_CKCTL:#ifdef ORIGINAL_CODE .word 0x110f#else .word 0x010f#endifVAL_DPLL1_CTL: .word 0x2710VAL_TC_EMIFS_CS1_CONFIG_PRELIM: .word 0x00001149VAL_TC_EMIFS_CS2_CONFIG_PRELIM: .word 0x00004158VAL_TC_EMIFS_CS0_CONFIG: .word 0x002130b0VAL_TC_EMIFS_CS1_CONFIG: .word 0x0000f559VAL_TC_EMIFS_CS2_CONFIG: .word 0x000055f0VAL_TC_EMIFS_CS3_CONFIG: .word 0x00003331VAL_TC_EMIFF_SDRAM_CONFIG: .word 0x010290fcVAL_TC_EMIFF_MRS: .word 0x00000027V_0xffffffff: .word 0xffffffff V_0x0000ff22: .word 0x0000ff22#endif // CYGONCE_HAL_PLATFORM_SETUP_H⌨️ 快捷键说明
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