var_io.h
来自「eCos操作系统源码」· C头文件 代码 · 共 599 行 · 第 1/2 页
H
599 行
#ifndef CYGONCE_HAL_VAR_IO_H#define CYGONCE_HAL_VAR_IO_H//=============================================================================//// var_io.h//// Variant specific registers////=============================================================================//####ECOSGPLCOPYRIGHTBEGIN####// -------------------------------------------// This file is part of eCos, the Embedded Configurable Operating System.// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.// Copyright (C) 2003 Nick Garnett <nickg@calivar.com>//// eCos is free software; you can redistribute it and/or modify it under// the terms of the GNU General Public License as published by the Free// Software Foundation; either version 2 or (at your option) any later version.//// eCos is distributed in the hope that it will be useful, but WITHOUT ANY// WARRANTY; without even the implied warranty of MERCHANTABILITY or// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License// for more details.//// You should have received a copy of the GNU General Public License along// with eCos; if not, write to the Free Software Foundation, Inc.,// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.//// As a special exception, if other files instantiate templates or use macros// or inline functions from this file, or you compile this file and link it// with other works to produce a work based on this file, this file does not// by itself cause the resulting work to be covered by the GNU General Public// License. However the source code for this file must still be made available// in accordance with section (3) of the GNU General Public License.//// This exception does not invalidate any other reasons why a work based on// this file might be covered by the GNU General Public License.//// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.// at http://sources.redhat.com/ecos/ecos-license/// -------------------------------------------//####ECOSGPLCOPYRIGHTEND####//=============================================================================//#####DESCRIPTIONBEGIN####//// Author(s): jskov// Contributors:jskov, gthomas, tkoeller, tdrury, nickg// Date: 2001-07-12// Purpose: AT91 variant specific registers// Description: // Usage: #include <cyg/hal/var_io.h>////####DESCRIPTIONEND####////=============================================================================#include <cyg/hal/plf_io.h>//=============================================================================// USART#ifndef AT91_USART0#define AT91_USART0 0xFFFD0000#endif#ifndef AT91_USART1#define AT91_USART1 0xFFFCC000#endif#define AT91_US_CR 0x00 // Control register#define AT91_US_CR_RxRESET (1<<2)#define AT91_US_CR_TxRESET (1<<3)#define AT91_US_CR_RxENAB (1<<4)#define AT91_US_CR_RxDISAB (1<<5)#define AT91_US_CR_TxENAB (1<<6)#define AT91_US_CR_TxDISAB (1<<7)#define AT91_US_CR_RSTATUS (1<<8)#define AT91_US_CR_STTTO (1<<11)#define AT91_US_MR 0x04 // Mode register#define AT91_US_MR_CLOCK 4#define AT91_US_MR_CLOCK_MCK (0<<AT91_US_MR_CLOCK)#define AT91_US_MR_CLOCK_MCK8 (1<<AT91_US_MR_CLOCK)#define AT91_US_MR_CLOCK_SCK (2<<AT91_US_MR_CLOCK)#define AT91_US_MR_LENGTH 6#define AT91_US_MR_LENGTH_5 (0<<AT91_US_MR_LENGTH)#define AT91_US_MR_LENGTH_6 (1<<AT91_US_MR_LENGTH)#define AT91_US_MR_LENGTH_7 (2<<AT91_US_MR_LENGTH)#define AT91_US_MR_LENGTH_8 (3<<AT91_US_MR_LENGTH)#define AT91_US_MR_SYNC 8#define AT91_US_MR_SYNC_ASYNC (0<<AT91_US_MR_SYNC)#define AT91_US_MR_SYNC_SYNC (1<<AT91_US_MR_SYNC)#define AT91_US_MR_PARITY 9#define AT91_US_MR_PARITY_EVEN (0<<AT91_US_MR_PARITY)#define AT91_US_MR_PARITY_ODD (1<<AT91_US_MR_PARITY)#define AT91_US_MR_PARITY_SPACE (2<<AT91_US_MR_PARITY)#define AT91_US_MR_PARITY_MARK (3<<AT91_US_MR_PARITY)#define AT91_US_MR_PARITY_NONE (4<<AT91_US_MR_PARITY)#define AT91_US_MR_PARITY_MULTI (6<<AT91_US_MR_PARITY)#define AT91_US_MR_STOP 12#define AT91_US_MR_STOP_1 (0<<AT91_US_MR_STOP)#define AT91_US_MR_STOP_1_5 (1<<AT91_US_MR_STOP)#define AT91_US_MR_STOP_2 (2<<AT91_US_MR_STOP)#define AT91_US_MR_MODE 14#define AT91_US_MR_MODE_NORMAL (0<<AT91_US_MR_MODE)#define AT91_US_MR_MODE_ECHO (1<<AT91_US_MR_MODE)#define AT91_US_MR_MODE_LOCAL (2<<AT91_US_MR_MODE)#define AT91_US_MR_MODE_REMOTE (3<<AT91_US_MR_MODE)#define AT91_US_MR_MODE9 17#define AT91_US_MR_CLKO 18#define AT91_US_IER 0x08 // Interrupt enable register#define AT91_US_IER_RxRDY (1<<0) // Receive data ready#define AT91_US_IER_TxRDY (1<<1) // Transmitter ready#define AT91_US_IER_RxBRK (1<<2) // Break received#define AT91_US_IER_ENDRX (1<<3) // Rx end#define AT91_US_IER_ENDTX (1<<4) // Tx end#define AT91_US_IER_OVRE (1<<5) // Rx overflow#define AT91_US_IER_FRAME (1<<6) // Rx framing error#define AT91_US_IER_PARITY (1<<7) // Rx parity#define AT91_US_IER_TIMEOUT (1<<8) // Rx timeout#define AT91_US_IER_TxEMPTY (1<<9) // Tx empty#define AT91_US_IDR 0x0C // Interrupt disable register#define AT91_US_IMR 0x10 // Interrupt mask register#define AT91_US_CSR 0x14 // Channel status register#define AT91_US_CSR_RxRDY 0x01 // Receive data ready#define AT91_US_CSR_TxRDY 0x02 // Transmit ready#define AT91_US_CSR_OVRE 0x20 // Overrun error#define AT91_US_CSR_FRAME 0x40 // Framing error#define AT91_US_RHR 0x18 // Receive holding register#define AT91_US_THR 0x1C // Transmit holding register#define AT91_US_BRG 0x20 // Baud rate generator#define AT91_US_RTO 0x24 // Receive time out#define AT91_US_TTG 0x28 // Transmit timer guard#define AT91_US_RPR 0x30 // Receive pointer register#define AT91_US_RCR 0x34 // Receive counter register#define AT91_US_TPR 0x38 // Transmit pointer register#define AT91_US_TCR 0x3c // Transmit counter register#define AT91_US_BAUD(baud) ((CYGNUM_HAL_ARM_AT91_CLOCK_SPEED/(8*(baud))+1)/2)//=============================================================================// PIO#ifndef AT91_PIO#define AT91_PIO 0xFFFF0000#endif#define AT91_PIO_PER 0x00 // PIO enable#define AT91_PIO_PDR 0x04 // PIO disable#define AT91_PIO_PSR 0x08 // PIO status#define AT91_PIO_PSR_TCLK0 0x00000001 // Timer #0 clock#define AT91_PIO_PSR_TIOA0 0x00000002 // Timer #0 signal A#define AT91_PIO_PSR_TIOB0 0x00000004 // Timer #0 signal B#define AT91_PIO_PSR_TCLK1 0x00000008 // Timer #1 clock#define AT91_PIO_PSR_TIOA1 0x00000010 // Timer #1 signal A#define AT91_PIO_PSR_TIOB1 0x00000020 // Timer #1 signal B#define AT91_PIO_PSR_TCLK2 0x00000040 // Timer #2 clock#define AT91_PIO_PSR_TIOA2 0x00000080 // Timer #2 signal A#define AT91_PIO_PSR_TIOB2 0x00000100 // Timer #2 signal B#define AT91_PIO_PSR_IRQ0 0x00000200 // IRQ #0#define AT91_PIO_PSR_IRQ1 0x00000400 // IRQ #1#define AT91_PIO_PSR_IRQ2 0x00000800 // IRQ #2#define AT91_PIO_PSR_FIQ 0x00001000 // FIQ#define AT91_PIO_PSR_SCK0 0x00002000 // Serial port #0 clock#define AT91_PIO_PSR_TXD0 0x00004000 // Serial port #0 TxD#define AT91_PIO_PSR_RXD0 0x00008000 // Serial port #0 RxD#define AT91_PIO_PSR_P16 0x00010000 // PIO port #16#define AT91_PIO_PSR_P17 0x00020000 // PIO port #17#define AT91_PIO_PSR_P18 0x00040000 // PIO port #18#define AT91_PIO_PSR_P19 0x00080000 // PIO port #19#define AT91_PIO_PSR_SCK1 0x00100000 // Serial port #1 clock#define AT91_PIO_PSR_TXD1 0x00200000 // Serial port #1 TxD#define AT91_PIO_PSR_RXD1 0x00400000 // Serial port #1 RxD#define AT91_PIO_PSR_P23 0x00800000 // PIO port #23#define AT91_PIO_PSR_P24 0x01000000 // PIO port #24#define AT91_PIO_PSR_MCKO 0x02000000 // Master clock out#define AT91_PIO_PSR_NCS2 0x04000000 // Chip select #2#define AT91_PIO_PSR_NCS3 0x08000000 // Chip select #3#define AT91_PIO_PSR_CS7_A20 0x10000000 // Chip select #7 or A20#define AT91_PIO_PSR_CS6_A21 0x20000000 // Chip select #6 or A21#define AT91_PIO_PSR_CS5_A22 0x40000000 // Chip select #5 or A22#define AT91_PIO_PSR_CS4_A23 0x80000000 // Chip select #4 or A23#define AT91_PIO_OER 0x10 // Output enable#define AT91_PIO_ODR 0x14 // Output disable#define AT91_PIO_OSR 0x18 // Output status#define AT91_PIO_IFER 0x20 // Input Filter enable#define AT91_PIO_IFDR 0x24 // Input Filter disable#define AT91_PIO_IFSR 0x28 // Input Filter status#define AT91_PIO_SODR 0x30 // Set out bits#define AT91_PIO_CODR 0x34 // Clear out bits#define AT91_PIO_ODSR 0x38 // Output data status#define AT91_PIO_PDSR 0x3C // Pin data status#define AT91_PIO_IER 0x40 // Interrupt enable#define AT91_PIO_IDR 0x44 // Interrupt disable#define AT91_PIO_IMR 0x48 // Interrupt mask#define AT91_PIO_ISR 0x4C // Interrupt status//=============================================================================// Advanced Interrupt Controller (AIC)#ifndef AT91_AIC#define AT91_AIC 0xFFFFF000#endif#define AT91_AIC_SMR0 ((0*4)+0x000)#define AT91_AIC_SMR1 ((1*4)+0x000)#define AT91_AIC_SMR2 ((2*4)+0x000)#define AT91_AIC_SMR3 ((3*4)+0x000)#define AT91_AIC_SMR4 ((4*4)+0x000)#define AT91_AIC_SMR5 ((5*4)+0x000)#define AT91_AIC_SMR6 ((6*4)+0x000)#define AT91_AIC_SMR7 ((7*4)+0x000)#define AT91_AIC_SMR8 ((8*4)+0x000)#define AT91_AIC_SMR9 ((9*4)+0x000)#define AT91_AIC_SMR10 ((10*4)+0x000)#define AT91_AIC_SMR11 ((11*4)+0x000)#define AT91_AIC_SMR12 ((12*4)+0x000)#define AT91_AIC_SMR13 ((13*4)+0x000)#define AT91_AIC_SMR14 ((14*4)+0x000)#define AT91_AIC_SMR15 ((15*4)+0x000)#define AT91_AIC_SMR16 ((16*4)+0x000)#define AT91_AIC_SMR17 ((17*4)+0x000)#define AT91_AIC_SMR18 ((18*4)+0x000)#define AT91_AIC_SMR19 ((19*4)+0x000)#define AT91_AIC_SMR20 ((20*4)+0x000)#define AT91_AIC_SMR21 ((21*4)+0x000)#define AT91_AIC_SMR22 ((22*4)+0x000)#define AT91_AIC_SMR23 ((23*4)+0x000)#define AT91_AIC_SMR24 ((24*4)+0x000)#define AT91_AIC_SMR25 ((25*4)+0x000)#define AT91_AIC_SMR26 ((26*4)+0x000)#define AT91_AIC_SMR27 ((27*4)+0x000)#define AT91_AIC_SMR28 ((28*4)+0x000)#define AT91_AIC_SMR29 ((29*4)+0x000)#define AT91_AIC_SMR30 ((30*4)+0x000)#define AT91_AIC_SMR31 ((31*4)+0x000)#define AT91_AIC_SMR_LEVEL_LOW (0<<5)#define AT91_AIC_SMR_LEVEL_HI (2<<5)#define AT91_AIC_SMR_EDGE_NEG (1<<5)#define AT91_AIC_SMR_EDGE_POS (3<<5)#define AT91_AIC_SMR_PRIORITY 0x07#define AT91_AIC_SVR0 ((0*4)+0x080)#define AT91_AIC_SVR1 ((1*4)+0x080)#define AT91_AIC_SVR2 ((2*4)+0x080)#define AT91_AIC_SVR3 ((3*4)+0x080)#define AT91_AIC_SVR4 ((4*4)+0x080)#define AT91_AIC_SVR5 ((5*4)+0x080)#define AT91_AIC_SVR6 ((6*4)+0x080)#define AT91_AIC_SVR7 ((7*4)+0x080)#define AT91_AIC_SVR8 ((8*4)+0x080)#define AT91_AIC_SVR9 ((9*4)+0x080)#define AT91_AIC_SVR10 ((10*4)+0x080)#define AT91_AIC_SVR11 ((11*4)+0x080)#define AT91_AIC_SVR12 ((12*4)+0x080)#define AT91_AIC_SVR13 ((13*4)+0x080)#define AT91_AIC_SVR14 ((14*4)+0x080)#define AT91_AIC_SVR15 ((15*4)+0x080)#define AT91_AIC_SVR16 ((16*4)+0x080)#define AT91_AIC_SVR17 ((17*4)+0x080)#define AT91_AIC_SVR18 ((18*4)+0x080)#define AT91_AIC_SVR19 ((19*4)+0x080)#define AT91_AIC_SVR20 ((20*4)+0x080)#define AT91_AIC_SVR21 ((21*4)+0x080)#define AT91_AIC_SVR22 ((22*4)+0x080)#define AT91_AIC_SVR23 ((23*4)+0x080)#define AT91_AIC_SVR24 ((24*4)+0x080)#define AT91_AIC_SVR25 ((25*4)+0x080)#define AT91_AIC_SVR26 ((26*4)+0x080)#define AT91_AIC_SVR27 ((27*4)+0x080)#define AT91_AIC_SVR28 ((28*4)+0x080)#define AT91_AIC_SVR29 ((29*4)+0x080)#define AT91_AIC_SVR30 ((30*4)+0x080)#define AT91_AIC_SVR31 ((31*4)+0x080)#define AT91_AIC_IVR 0x100#define AT91_AIC_FVR 0x104#define AT91_AIC_ISR 0x108#define AT91_AIC_IPR 0x10C#define AT91_AIC_IMR 0x110#define AT91_AIC_CISR 0x114#define AT91_AIC_IECR 0x120#define AT91_AIC_IDCR 0x124#define AT91_AIC_ICCR 0x128#define AT91_AIC_ISCR 0x12C#define AT91_AIC_EOI 0x130#define AT91_AIC_SVR 0x134//=============================================================================// Timer / counter#ifndef AT91_TC#define AT91_TC 0xFFFE0000#endif#define AT91_TC_TC0 0x00#define AT91_TC_CCR 0x00#define AT91_TC_CCR_CLKEN 0x01#define AT91_TC_CCR_CLKDIS 0x02#define AT91_TC_CCR_TRIG 0x04#define AT91_TC_CMR 0x04// Capture mode definitions#define AT91_TC_CMR_CLKS 0⌨️ 快捷键说明
复制代码Ctrl + C
搜索代码Ctrl + F
全屏模式F11
增大字号Ctrl + =
减小字号Ctrl + -
显示快捷键?