hal_platform_setup.h

来自「eCos操作系统源码」· C头文件 代码 · 共 560 行 · 第 1/2 页

        cmp     r4,#0
        bne     50b
        mov     pc,lr

hexR6:  
        PutHex4 r6
        PutC    ' '
        mov     pc,lr        
54:             
#endif // DEBUG_INIT

        // Disable all interrupts
        ldr     r1,=SA11X0_ICMR
        mov     r0,#0
        str     r0,[r1]

        // Make sure MMU is OFF
	mov r0,#0xE0000000	// Force cache writeback by reloading
	add r2,r0,#0x4000	// cache from the zeros bank
123:    ldr r1,[r0],#32
	cmp r0, r2
	bne 123b
	mov r0,#0
	mov r1,#0x0070		// MMU Control System bit
	mcr p15,0,r0,c7,c7,0	// Flush data and instruction cache
	mcr p15,0,r0,c8,c7,0	// Flush ID TLBs
	mcr p15,0,r0,c9,c0,0	// Flush Read-Buffer
	mcr p15,0,r0,c7,c10,4	// Drain write buffer
	mcr p15,0,r0,c13,c0,0	// Disable virtual ID mapping
	mcr p15,0,r1,c1,c0,0	// Write MMU control register
	nop; nop; nop; nop

        InitUART3
#ifdef DEBUG_INIT        
        mov     r7,#5
05:     PutC    '\n'
        PutC    '\r'
        sub     r7,r7,#1
        cmp     r7,#0
        bne     05b

        mrs     r6,cpsr
        bl      hexR6
#endif // DEBUG_INIT
        
#if 0 // This made no difference        
        ldr     r1,=10f
        ldr     r2,=SA11X0_RAM_BANK0_BASE
        add     r1,r1,r2
        mov     r0,#(CPSR_IRQ_DISABLE|CPSR_FIQ_DISABLE|CPSR_SUPERVISOR_MODE)
        msr     cpsr,r0
        msr     spsr,r0
        movs    pc,r1
10:             
#else
                        
        mov     r0,#(CPSR_IRQ_DISABLE|CPSR_FIQ_DISABLE|CPSR_SUPERVISOR_MODE)
        msr     cpsr,r0
#endif
#ifdef DEBUG_INIT
        mrs     r6,cpsr
        bl      hexR6

        ldr     r5,=0x00000000
        ldr     r4,=0x100/32
        bl      dump
#endif // DEBUG_INIT

        // Initialise extended GPIO
        ldr     r0,=SA1110_EGPIO
        ldr     r4,=SA1110_EIO_MIN

	// Initialize pin directions
	ldr	r1,=SA11X0_GPIO_PIN_DIRECTION
	ldr	r2,=0x0401F3FC
	str	r2,[r1]

	ldr	r2,[r1,#4]
	tst	r2,#0x08000000	// Look for expansion pack
	orreq	r4,r4,#0x01B0	// Power it up if there
	str	r4,[r0]

#if defined(CYG_HAL_STARTUP_ROM)
        // Disable clock switching
        mcr     p15,0,r0,\
                SA11X0_TEST_CLOCK_AND_IDLE_REGISTER,\
                SA11X0_DISABLE_CLOCK_SWITCHING_RM,\
                SA11X0_DISABLE_CLOCK_SWITCHING_OPCODE

        // Set up processor clock
        ldr     r1,=SA11X0_PWR_MGR_PLL_CONFIG
        ldr     r2,=SA11X0_PLL_CLOCK
        str     r2,[r1]

        // Turn clock switching back on
        mcr     p15,0,r0,\
                SA11X0_TEST_CLOCK_AND_IDLE_REGISTER,\
                SA11X0_ENABLE_CLOCK_SWITCHING_RM,\
                SA11X0_ENABLE_CLOCK_SWITCHING_OPCODE
        nop
        nop
#endif
        
        // Pause
        ldr     r1,=100000
10:     sub     r1,r1,#1
        cmp     r1,#0
        bne     10b        

#ifdef CYGBLD_HAL_STARTUP_ROM_INIT_DRAM
        
        // Initialize DRAM controller
        bl      19f
// DRAM controller initialization        
dram_table:
        .word   SA11X0_DRAM0_CAS_0,           0xAAAAAAA7
        .word   SA11X0_DRAM0_CAS_1,           0xAAAAAAAA
        .word   SA11X0_DRAM0_CAS_2,           0xAAAAAAAA
//        .word   SA11X0_STATIC_CONTROL_0,      0x4B384B38
//        .word   SA11X0_STATIC_CONTROL_1,      0x22212419
        .word   SA11X0_EXP_BUS_CONFIGURATION, 0x994A994A  // 0x90E790E7
        .word   SA11X0_REFRESH_CONFIGURATION, 0x00302001
        .word   SA11X0_DRAM2_CAS_0,           0xAAAAAAA7
        .word   SA11X0_DRAM2_CAS_1,           0xAAAAAAAA
        .word   SA11X0_DRAM2_CAS_2,           0xAAAAAAAA
//        .word   SA11X0_STATIC_CONTROL_2,      0x42194449
        .word   SA11X0_SMROM_CONFIGURATION,   0x00000000  // 0xAFCCAFCC
        .word   SA11X0_DRAM_CONFIGURATION,    0x0000F354  // 0x72547254        // Disabled
        .word   0, 0

19:     mov     r1,lr                           // Points to 'dram_table'        
        ldr     r2,[r1],#4                      // First control register
20:     ldr     r3,[r1],#4
        str     r3,[r2]
        ldr     r2,[r1],#4                      // Next control register
        cmp     r2,#0
        bne     20b

        // Enable UART
        ldr     r1,=SA1110_GPCLK_CONTROL_0
        ldr     r2,=SA1110_GPCLK_SUS_UART
        str     r2,[r1]

        // Release DRAM hold (set by RESET)
        ldr     r1,=SA11X0_PWR_MGR_SLEEP_STATUS
        ldr     r2,=SA11X0_DRAM_CONTROL_HOLD
        str     r2,[r1]

        // Perform 8 reads from unmapped/unenabled DRAM
        ldr     r1,=SA11X0_RAM_BANK0_BASE
        ldr     r2,[r1]
        ldr     r2,[r1]
        ldr     r2,[r1]
        ldr     r2,[r1]
        ldr     r2,[r1]
        ldr     r2,[r1]
        ldr     r2,[r1]
        ldr     r2,[r1]

        // Enable DRAM controller
        ldr     r1,=SA11X0_DRAM_CONFIGURATION
        ldr     r2,=0x0000F355   // 0x72547255
        str     r2,[r1]

#endif // CYGBLD_HAL_STARTUP_ROM_INIT_DRAM
        
        // Release peripheral hold (set by RESET)
        ldr     r1,=SA11X0_PWR_MGR_SLEEP_STATUS
        ldr     r2,=SA11X0_PERIPHERAL_CONTROL_HOLD
        str     r2,[r1]

        // Wakeup (via power/resume button)
        ldr     r1,=SA11X0_RESET_STATUS
        ldr     r2,[r1]
        cmp     r2,#SA11X0_SLEEP_MODE_RESET
        bne     45f
        ldr     r1,=SA11X0_PWR_MGR_SCRATCHPAD
        ldr     r1,[r1]
        mov     pc,r1
        nop
45:     nop        

        // Set up a stack [for calling C code]
        ldr     r1,=__startup_stack
        ldr     r2,=SA11X0_RAM_BANK0_BASE
        orr     sp,r1,r2

#ifdef DEBUG_INIT
        mrc     p15,0,r6,c1,c0,0
        bl      hexR6
        mrc     p15,0,r6,c2,c0,0
        bl      hexR6
        mrc     p15,0,r6,c3,c0,0
        bl      hexR6

        mrc     p15,0,r5,c2,c0,0
        ldr     r6,=0xFFFFC000
        and     r5,r5,r6
        ldr     r4,=0x100/32
        bl      dump
#endif // DEBUG_INIT
        
        // Create MMU tables
        bl      hal_mmu_init

#ifdef DEBUG_INIT
        ldr     r5,=0x00000000
        ldr     r4,=0x100/32
        bl      dump

        ldr     r5,=0xC0020000
        ldr     r4,=0x100/32
        bl      dump

        mrc     p15,0,r5,c2,c0,0
        ldr     r6,=0xFFFFC000
        and     r5,r5,r6
//        ldr     r4,=0x4000/32
        ldr     r4,=0x100/32
        bl      dump
#endif // DEBUG_INIT
        
        // Enable MMU
        ldr     r2,=10f
       	ldr	r1,=MMU_Control_Init|MMU_Control_M
	mcr	MMU_CP,0,r1,MMU_Control,c0
        mov     pc,r2
        mcr     MMU_CP,0,r0,MMU_InvalidateCache,c7,0	// Flush data and instruction cache
	mcr     MMU_CP,0,r0,MMU_TLB,c7,0        	// Flush ID TLBs
10:     
        nop
        nop
        nop

#ifdef DEBUG_INIT
        ldr     r5,=0x00022000
        ldr     r4,=0xDEADDEAD
        str     r4,[r5],#4
        str     r4,[r5],#4
        str     r4,[r5],#4
        str     r4,[r5],#4

        ldr     r5,=0x00022000
        ldr     r4,=0x100/32
        bl      dump
#endif // DEBUG_INIT
        
        // Save shadow copy of BCR
        ldr     r1,=_ipaq_EGPIO
#ifdef DEGUG_INIT
        ldr     r4,=SA1110_EIO_MIN
#endif // DEBUG_INIT
        str     r4,[r1]
        .endm

#if defined(CYG_HAL_STARTUP_Compaq)
#define CYG_HAL_STARTUP_ROM
#define CYG_HAL_ROM_RESET_USES_JUMP
#endif

#else // defined(CYG_HAL_STARTUP_ROM)
#define PLATFORM_SETUP1
#endif

#define PLATFORM_VECTORS         _platform_vectors
        .macro  _platform_vectors
        .globl  _ipaq_EGPIO
_ipaq_EGPIO:    .long   0       // Extended GPIO shadow

        .globl  _ipaq_LCD_params
_ipaq_LCD_params:       
        .short  0,0,0,0         // Coordinates used by virtual keyboard
        .short  0,0,0,0
        .short  0               // Checksum of above        
        .endm                                        

/*---------------------------------------------------------------------------*/
/* end of hal_platform_setup.h                                               */
#endif /* CYGONCE_HAL_PLATFORM_SETUP_H */