hal_edb7xxx.h

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#endif
#define INTMR3  0x80002280 // Interrupt mask #3

#define UARTDR1 0x80000480 // UART #1 data register
#define UARTDR2 0x80001480 // UART #2 data register
#define UBLCR1  0x800004C0 // UART #1 baud rate / line control
#define UBLCR2  0x800014C0 // UART #2 baud rate / line control
#define UBLCR_BRDV    0xFFF   // Baud rate
#define UBLCR_BREAK   (1<<12) // Generate break signal
#define UBLCR_PRTEN   (1<<13) // Enable parity
#define UBLCR_EVENPRT (1<<14) // 1=even parity, 0=odd
#define UBLCR_XSTOP   (1<<15) // 0=1 stop bit, 1=2 stop bits
#define UBLCR_FIFOEN  (1<<16) // Enable Tx/Rx FIFOs
#define UBLCR_WRDLEN  (3<<17) // Word (character) length field
#define UBLCR_WRDLEN5 (0<<17)
#define UBLCR_WRDLEN6 (1<<17)
#define UBLCR_WRDLEN7 (2<<17)
#define UBLCR_WRDLEN8 (3<<17)
#define UART_DIVISOR  230400
#define UART_BITRATE(baud) ((UART_DIVISOR/(baud))-1)
#if 90317 == CYGHWR_HAL_ARM_EDB7XXX_PROCESSOR_CLOCK
#undef UART_DIVISOR
// The speed enhancement is 22.5%
#define UART_DIVISOR  (230400 * 1225/1000)
#endif

#define MEMCFG1 0x80000180 // Memory configuration register #1
#define MEMCFG2 0x800001C0 // Memory configuration register #2

#define DRFPR   0x80000200 // DRAM refresh period

#define LCDCON                0x800002C0  // LDC control
#define LCDCON_BUFSIZ         0x00001FFF  // Video buffer size
#define LCDCON_BUFSIZ_S       0           // Position of buffer size
#define LCDCON_LINE_LENGTH    0x0007E000  // Line length
#define LCDCON_LINE_LENGTH_S  13          // Position of line length
#define LCDCON_PIX_PRESCALE   0x01F80000  // Pixel prescale value
#define LCDCON_PIX_PRESCALE_S 19          // Position of prescale value
#define LCDCON_AC_PRESCALE    0x3E000000  // LCD AC bias frequency
#define LCDCON_AC_PRESCALE_S  25          // Position to AC bias
#define LCDCON_GSEN           0x40000000  // Enable greyscale
#define LCDCON_GSMD           0x80000000  // Greyscale mode
                                          // 00 - 1bpp, 01 - 2bpp, 11 - 4 bpp

#define TC1D    0x80000300 // Timer/Counter #1 register
#define TC2D    0x80000340 // Timer/Counter #2 register
#define RTCDR   0x80000380 // Real time clock data register
#define RTCMR   0x800003C0 // Real time clock match register

#define PMPCON  0x80000400 // DC-DC pump control

#define CODR    0x80000440 // CODEC data register

#define SYNCIO  0x80000500 // Synchronous I/O data register

#define PALLSW  0x80000540 // LCD palette - LSW (Pixel values 0..7)
#define PALMSW  0x80000580 // LCD palette - MSW (Pixel values 8..15)

#define STFCLR  0x800005C0 // Clear startup reason flags
#define BLEOI   0x80000600 // Clear battery low interrupt
#define MCEOI   0x80000640 // Clear media changed interrupt
#define TEOI    0x80000680 // Clear tick/watchdog interrupt
#define TC1EOI  0x800006C0 // Clear timer/counter #1 interrupt
#define TC2EOI  0x80000700 // Clear timer/counter #2 interrupt
#define RTCEOI  0x80000740 // Clear real time clock interrupt
#define UMSEOI  0x80000780 // Clear UART modem status change interrupt
#define COEOI   0x800007C0 // Clear CODEC sound interrupt

#define HALT    0x80000800 // Enter 'idle' state
#define STDBY   0x80000840 // Enter 'standby' state

#define FRBADDR 0x80001000 // LCD frame buffer start

#define SNZDISP 0x800012C0 // Snooze display size

#define SS2DR   0x80001500 // Master/slave SSI2 register

#define SRXEOF  0x80001600 // Clear Rx FIFO overflow flag
#define SS2POP  0x800016C0 // Pop SSI2 residual byte into FIFO

#define KBDEOI  0x80001700 // Clear keyboard interrupt

#define SNOOZE  0x80001800 // Enter 'snooze' state

#if defined(__EDB7211)
#define MCCR    0x80002000 // MCP control register
#define MCDR0   0x80002040 // MCP data register #0
#define MCDR1   0x80002080 // MCP data register #1
#define MCDR2   0x800020C0 // MCP data register #2
#define MCSR    0x80002100 // MCP status register
#endif

#if defined(__EDB7209) || \
defined(__EDB7312) || \
1

#define I2S_CTL         0x80002000 // I2S (Audio interface) control
#define I2S_CTL_FLAG    0x0404     // Magic
#define I2S_CTL_EN      (1<<16)    // Enable interface
#define I2S_CTL_ECS     (1<<17)    // External clock select
#define I2S_CTL_LCTM    (1<<19)    // Left channel transmit interrupt
#define I2S_CTL_LCRM    (1<<20)    // Left channel receive interrupt
#define I2S_CTL_RCTM    (1<<21)    // Right channel transmit interrupt
#define I2S_CTL_RCRM    (1<<22)    // Right channel receive interrupt
#if defined(__EDB7209)
#define I2S_CTL_LBM     (1<<23)    // Loop-back mode
#endif
#define I2S_RIGHT_FIFO  0x80002040 // Right channel FIFO access
#define I2S_LEFT_FIFO   0x80002080 // Left channel FIFO access
#define I2S_FIFO_CTL    0x800020C0 // FIFO control
#define I2S_FIFO_CTL_RIGHT_ENABLE  0x00118000
#define I2S_FIFO_CTL_RIGHT_DISABLE 0x00110000
#define I2S_FIFO_CTL_LEFT_ENABLE   0x000D8000
#define I2S_FIFO_CTL_LEFT_DISABLE  0x000D0000
#define I2S_STAT        0x80002100 // I2S interface status
#define I2S_STAT_RCTSR  (1<<0)     // Right channel transmit service request
#define I2S_STAT_RCRSR  (1<<1)     // Right channel receive service request
#define I2S_STAT_LCTSR  (1<<2)     // Left channel transmit service request
#define I2S_STAT_LCRSR  (1<<3)     // Left channel receive service request
#define I2S_STAT_RCTUR  (1<<4)     // Right channel transmit FIFO underrun
#define I2S_STAT_RCROR  (1<<5)     // Right channel receive FIFO overrun
#define I2S_STAT_LCTUR  (1<<6)     // Left channel transmit FIFO underrun
#define I2S_STAT_LCROR  (1<<7)     // Left channel receive FIFO overrun
#define I2S_STAT_RCTNF  (1<<8)     // Right channel transmit FIFO not full
#define I2S_STAT_RCRNE  (1<<9)     // Right channel receive FIFO not empty
#define I2S_STAT_LCTNF  (1<<10)    // Left channel transmit FIFO not full
#define I2S_STAT_LCRNE  (1<<11)    // Left channel receive FIFO not empty
#define I2S_STAT_FIFO   (1<<12)    // A FIFO operation has completed
#endif

#ifdef __EDB7312
// If DAI_ headers wishes to be used instead (for consistency)
#define DAI_CTL       I2S_CTL
#define DAI_CTL_FLAG  I2S_CTL_FLAG
#define DAI_CTL_EN    I2S_CTL_EN
#define DAI_CTL_ECS   I2S_CTL_ECS
#define DAI_CTL_LCTM  I2S_CTL_LCTM
#define DAI_CTL_LCRM  I2S_CTL_LCRM
#define DAI_CTL_RCTM  I2S_CTL_RCTM
#define DAI_CTL_RCRM  I2S_CTL_RCRM

#define DAI_RIGHT_FIFO  I2S_RIGHT_FIFO
#define DAI_LEFT_FIFO   I2S_LEFT_FIFO

#define DAI_FIFO_CTL                I2S_FIFO_CTL
#define DAI_FIFO_CTL_RIGHT_ENABLE   I2S_FIFO_CTL_RIGHT_ENABLE
#define DAI_FIFO_CTL_RIGHT_DISABLE  I2S_FIFO_CTL_RIGHT_DISABLE
#define DAI_FIFO_CTL_LEFT_ENABLE    I2S_FIFO_CTL_LEFT_ENABLE
#define DAI_FIFO_CTL_LEFT_DISABLE   I2S_FIFO_CTL_LEFT_DISABLE

#define DAI_STAT        I2S_STAT
#define DAI_STAT_RCTSR  I2S_STAT_RCTSR
#define DAI_STAT_RCRSR  I2S_STAT_RCRSR
#define DAI_STAT_LCTSR  I2S_STAT_LCTSR
#define DAI_STAT_LCRSR  I2S_STAT_LCRSR
#define DAI_STAT_RCTUR  I2S_STAT_RCTUR
#define DAI_STAT_RCROR  I2S_STAT_RCROR
#define DAI_STAT_LCTUR  I2S_STAT_LCTUR
#define DAI_STAT_LCROR  I2S_STAT_LCROR
#define DAI_STAT_RCTNF  I2S_STAT_RCTNF
#define DAI_STAT_RCRNE  I2S_STAT_RCRNE
#define DAI_STAT_LCTNF  I2S_STAT_LCTNF
#define DAI_STAT_LCRNE  I2S_STAT_LCRNE
#define DAI_STAT_FIFO   I2S_STAT_FIFO

// Additional 7312 register
#define DAI_MODE        0x80002600  // I2S mode control register
#define DAI_MODE_I2SF64  (1<<0)     // Frame size
#define DAI_MODE_CLKEN   (1<<1)     // Enable audio clock generator
#define DAI_MODE_CLKSRC  (1<<2)     // Select audio clock source
#define DAI_MODE_MCLK    (1<<3)     // Enables MCLK (BUZ) (256 frame size)
#define DAI_MODE_LBM     (1<<5)     // Loopback mode

#define DAI_MODE_AUDDIV_MASK  0x7F00  // Mask for the frequency divisor
                                      //    for the sample frequency and
                                      //    bit clock

#define SYSCON3_I2SSEL SYSCON3_DAISEL  // Backward compatiblity
                                       //    for sample i2s_audio_fiq.s

#define INTSR3_I2SINT INTSR3_DAIINT  // Backward compatiblity
                                     //    for sample i2s_audio_fiq.s


// Further additional 7312 register for special 90MHz variant:
// PLL_Multiplier_Register 0x80002610  - the location of the PLL multiplier register
// Value_For_90_MHz_Operation 0x31000000
#define EP7312_PLL_MR            0x80002610
#define EP7312_PLL_MR_FOR_90MHz  0x31000000

#endif

#define LEDFLSH 0x800022C0 // LED flash control
#define LEDFLSH_ENABLE      (1<<6)      // LED enabled
#define LEDFLSH_DUTY(n)     ((n-1)<<2)  // LED on ratio
#define LEDFLSH_PERIOD(n)   (n-1)       // LED active time (1..4)

#define KBD_PORT 0x30010000 // Extra 8 bits of keyboard data

/*---------------------------------------------------------------------------*/
/* end of hal_edb7xxx.h                                                         */
#endif /* CYGONCE_HAL_EDB7XXX_H */