xscale_test.c

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//=============================================================================
//
//      xscale_test.c - Cyclone Diagnostics
//
//=============================================================================
//####ECOSGPLCOPYRIGHTBEGIN####
// -------------------------------------------
// This file is part of eCos, the Embedded Configurable Operating System.
// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
//
// eCos is free software; you can redistribute it and/or modify it under
// the terms of the GNU General Public License as published by the Free
// Software Foundation; either version 2 or (at your option) any later version.
//
// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or
// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
// for more details.
//
// You should have received a copy of the GNU General Public License along
// with eCos; if not, write to the Free Software Foundation, Inc.,
// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
//
// As a special exception, if other files instantiate templates or use macros
// or inline functions from this file, or you compile this file and link it
// with other works to produce a work based on this file, this file does not
// by itself cause the resulting work to be covered by the GNU General Public
// License. However the source code for this file must still be made available
// in accordance with section (3) of the GNU General Public License.
//
// This exception does not invalidate any other reasons why a work based on
// this file might be covered by the GNU General Public License.
//
// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
// at http://sources.redhat.com/ecos/ecos-license/
// -------------------------------------------
//####ECOSGPLCOPYRIGHTEND####
//=============================================================================
//#####DESCRIPTIONBEGIN####
//
// Author(s):   Scott Coulter, Jeff Frazier, Eric Breeden
// Contributors:
// Date:        2001-01-25
// Purpose:     
// Description: 
//
//####DESCRIPTIONEND####
//
//===========================================================================*/

/************************************************************************/
/* iq80310_test.c - Main diagnostics for IQ80310 board			*/
/*									*/
/* Modification History							*/
/* --------------------							*/
/* 11oct00, ejb, Created for IQ80310 StrongARM2				*/
/* 18dec00  jwf                                                         */
/* 02feb01  jwf	added tests: _coy_tight_loop, cache_loop, LoopMemTest,  */
/*              special_mem_test written by snc				*/     
/* 07feb01  jwf added function calls to a variable delay time generator */
/* 09feb01  jwf added function version_info to show version information */
/*              about OS, BOARD, CPLD, 80200 ID, 80312 ID.              */
/************************************************************************/

#include <redboot.h>
#include <cyg/io/pci_hw.h>
#include <cyg/io/pci.h>

#include "7_segment_displays.h"
#include "test_menu.h"
#include "iq80310.h"
#include "pci_bios.h"

extern void __disableDCache(void);
extern void __enableDCache(void);
extern void _enableFiqIrq(void);
extern void _usec_delay(void);
extern void _msec_delay(void);
extern void _enable_timer(void);
extern void _disable_timer(void);
extern int  xgetchar_timeout(char *ch, int msec);
extern char xgetchar(void);


/* 02/02/01 jwf */
extern long decIn(void);
extern long hexIn(void);
extern void hex32out(unsigned long num);
extern char* sgets(char *s);

extern void flash_test(MENU_ARG arg) RAM_FUNC_SECT;

extern STATUS pci_isr_connect (int intline, int bus, int device, int (*handler)(int), int arg);
extern STATUS pci_to_xint(int device, int intpin, int *xint);
extern void timer_test (MENU_ARG arg);

extern void delay_ms(int msecs);

extern int memTest (long startAddr, long endAddr);

/* 02/02/01 jwf */
extern int LoopMemTest (long	startAddr, long	endAddr);

extern void uart_test(MENU_ARG arg);
extern void pci_ether_test (UINT32 busno, UINT32 devno, UINT32 funcno);
extern void config_ints(void);	/* configure interrupts */
extern int eeprom_write (unsigned long pci_base, int eeprom_addr, unsigned short *p_data, int nwords);
extern int enable_external_interrupt (int int_id);
extern int disable_external_interrupt (int int_id);
extern int isr_connect(int int_num, void (*handler)(int), int arg);
extern int isr_disconnect(int int_num);
extern void init_external_timer(void);
extern void uninit_external_timer(void);
extern int isHost(void);

void pci_int_test (MENU_ARG arg);
void hdwr_diag (void);
void rotary_switch (MENU_ARG arg);
void seven_segment_display (MENU_ARG arg);
void backplane_detection(MENU_ARG arg);
void battery_status(MENU_ARG arg);
void ether_test (MENU_ARG arg);
void gpio_test (MENU_ARG arg);

/* 02/02/01 jwf */
void static cache_loop (MENU_ARG arg);

/* 02/09/01 jwf */
void version_info (MENU_ARG arg);
void read_coyanosa_id_reg (void);
char board_revision (void);

static void battery_test_menu (MENU_ARG arg);
static void battery_test_write (MENU_ARG arg);
static void battery_test_read (MENU_ARG arg);

/* 01/11/01 jwf */
void select_host_test_system (void);

void internal_timer(MENU_ARG arg);
static void enet_setup (MENU_ARG arg);
static void memory_tests (MENU_ARG arg);
static void repeat_mem_test (MENU_ARG arg);

/* 02/02/01 jwf */
static void special_mem_test (MENU_ARG arg);

static void spci_tests (MENU_ARG arg), ppci_tests (MENU_ARG arg);

#define VENDOR_INTEL    0x8086
#define INTEL_NAME	"Intel Corporation Inc."

#define I80303_BRIDGE	0x0309
#define I80303_NAME0	"80303 PCI-PCI Bridge"

#define I80303_ATU	0x5309
#define I80303_NAME1	"80303 Address Translation Unit"

#define I82557		0x1229
#define I82557_NAME	"82557/82558/82559 10/100 LAN Controller"

#define I82559ER	0x1209
#define I82559ER_NAME	"82559ER 10/100 LAN Controller"


/* Test Menu Table */
static MENU_ITEM testMenu[] = {
    {"Memory Tests",				memory_tests,	      0},
    {"Repeating Memory Tests",			repeat_mem_test,      0},
    {"16C552 DUART Serial Port Tests", 		uart_test, 	      0},
    {"Rotary Switch S1 Test",			rotary_switch,	      0},
    {"7 Segment LED Tests",			seven_segment_display,0},
    {"Backplane Detection Test",		backplane_detection,  0},
    {"Battery Status Test",			battery_status,       0},
    {"External Timer Test",			timer_test,           0},
#ifdef CYGPKG_IO_FLASH
    {"Flash Test",				flash_test,	      0},
#endif
    {"i82559 Ethernet Configuration",		enet_setup,	      0},
    {"i82559 Ethernet Test",			ether_test,	      0},
    {"i960Rx/303 PCI Interrupt Test",		pci_int_test,	      0},
    {"Internal Timer Test",			internal_timer,	      0},
    {"Secondary PCI Bus Test",			spci_tests,	      0},
    {"Primary PCI Bus Test",			ppci_tests,	      0},
    {"Battery Backup SDRAM Memory Test",	battery_test_menu,    0},
    {"GPIO Test",				gpio_test,	      0},
/* 02/02/01 jwf */
    {"Repeat-On-Fail Memory Test",		special_mem_test,     0},
    {"Coyonosa Cache Loop (No return)",		cache_loop,	      0},
/* 02/09/01 jwf */
    {"Show Software and Hardware Revision",	version_info,	      0}
};

#define NUM_MENU_ITEMS	(sizeof (testMenu) / sizeof (testMenu[0]))

#define MENU_TITLE	"\n  IQ80310 Hardware Tests"

extern void __reset(void);

void hdwr_diag (void)
{
    unsigned char* led0 = (unsigned char*)MSB_DISPLAY_REG;
    unsigned char* led1 = (unsigned char*)LSB_DISPLAY_REG;

    *led0 = LETTER_S;
    *led1 = LETTER_S;

    printf ("Entering Hardware Diagnostics - Disabling Data Cache!\n\n");

    __disableDCache();
	
    _enableFiqIrq(); /* enable FIQ and IRQ interrupts */
	 
    config_ints();  /* configure interrupts for diagnostics */

    /* 01/11/01 jwf */
    select_host_test_system();
	
    menu (testMenu, NUM_MENU_ITEMS, MENU_TITLE, MENU_OPT_NONE);

    printf ("Exiting Hardware Diagnostics - Reenabling Data Cache!\n\n");

    *led0 = ZERO;
    *led1 = ZERO;

    __reset();  /* reset the board so RedBoot starts with a clean slate */
}

/* 02/02/01 jwf */
static void cache_loop (MENU_ARG arg)
{
    printf ("Putting Processor in a Tight Loop Forever...\n\n");

    asm ( "0: mov r0,r0\n"
	  "b 0b\n");
    /* not reached */
}


/************************************************/
/* Secondary PCI Bus Test			*/
/*						*/
/* This test assumes that a IQ80303 eval board  */
/* is installed in a secondary PCI slot. This   */
/* second board must be configured with 32 Meg  */
/* of SDRAM minimum.		                */
/*						*/
/************************************************/
static void spci_tests (MENU_ARG arg)
{
    long  start_addr;
    long  mem_size;
    long  end_addr;
    cyg_pci_device_id  devid = CYG_PCI_NULL_DEVID;
    int bus, devfn;

    /* Look for ATU on the secondary PCI Bus */
    printf("\nLooking for a IQ80303 board on the Secondary PCI bus:\n");
    while (TRUE) {
	if (cyg_pci_find_device(VENDOR_INTEL, I80303_ATU, &devid)) {
	    bus = CYG_PCI_DEV_GET_BUS(devid);
	    devfn = CYG_PCI_DEV_GET_DEVFN(devid);
	    if (bus != SECONDARY_BUS_NUM)
		continue;
	    printf("An IQ80303 board has been detected: bus[%d] devive[%d] fn[%d].",
		   bus, CYG_PCI_DEV_GET_DEV(devfn), CYG_PCI_DEV_GET_FN(devfn));
	    break;
	} else {
	    printf("No IQ80303 board detected on the SPCI bus!\n");
	    return;
	}
    }

    /* read the PCI address which corresponds to the start of DRAM */
    cyg_pci_read_config_uint32(devid, 0x10, (UINT32 *)&start_addr);

    /* strip off indicator bits */
    start_addr &= 0xfffffff0;

    printf ("i80303 DRAM starts at PCI address 0x%08X\n", start_addr);

    /* skip over 1st Mbyte of target DRAM */
    start_addr += 0x100000;

    mem_size = 0x1f00000;
    end_addr = start_addr + mem_size;

    printf("\n\nTesting memory from $");
    hex32out(start_addr);
    printf(" to $");
    hex32out(end_addr);
    printf(".\n");

    memTest(start_addr, end_addr);
    printf("\n");

    printf ("\nMemory test done.\n");
    printf ("Press return to continue.\n");
    (void) hexIn();
}

/************************************************/
/* Primary PCI Bus Test			        */
/*						*/
/* This test assumes that a IQ80303 eval board  */
/* is installed in a primary PCI slot. This     */
/* second board must be configured with 32 Meg  */
/* of SDRAM minimum.				*/
/*						*/
/************************************************/
static void ppci_tests (MENU_ARG arg)
{
    long	start_addr;
    long	mem_size;
    long	end_addr;
    cyg_pci_device_id  devid = CYG_PCI_NULL_DEVID;
    int bus, devfn;

    /* check to see if we are the host of the backplane, if not 
       return an error */
    if (isHost() == FALSE) {
	printf ("Invalid test configuration, must be PCI host!\n");
	return;
    }

    /* Look for ATU on the primary PCI Bus */
    printf("\nLooking for a IQ80303 board on the Primary PCI bus:\n");
    while (TRUE) {
	if (cyg_pci_find_device(VENDOR_INTEL, I80303_ATU, &devid)) {
	    bus = CYG_PCI_DEV_GET_BUS(devid);
	    devfn = CYG_PCI_DEV_GET_DEVFN(devid);
	    if (bus != PRIMARY_BUS_NUM)
		continue;
	    printf("An IQ80303 board has been detected: bus[%d] devive[%d] fn[%d].",
		   bus, CYG_PCI_DEV_GET_DEV(devfn), CYG_PCI_DEV_GET_FN(devfn));
	    break;
	} else {
	    printf("No IQ80303 board detected on the PPCI bus!\n");
	    return;
	}
    }

    /* read the PCI address which corresponds to the start of DRAM */
    cyg_pci_read_config_uint32(devid, 0x10, (UINT32 *)&start_addr);

    /* strip off indicator bits */
    start_addr &= 0xfffffff0;

    printf ("i80303 DRAM starts at PCI address 0x%08X\n", start_addr);

    /* skip over 1st Mbyte of target DRAM */
    start_addr += 0x100000;

    mem_size = 0x1f00000;
    end_addr = start_addr + mem_size;

    printf("\n\nTesting memory from $");
    hex32out(start_addr);
    printf(" to $");