iop310_misc.c

来自「eCos操作系统源码」· C语言 代码 · 共 1,006 行 · 第 1/3 页

    *pfreq = i;
    *pperiod = newp;

    if ( do_set_hw ) {
        hal_clock_initialize( newp );
    }
}

// This routine is called during a clock interrupt.

void hal_clock_reset(cyg_uint32 vector, cyg_uint32 period)
{
    // to clear the timer interrupt, clear the timer interrupt
    // enable, then re-set the int. enable bit
    EXT_TIMER_INT_DISAB();
    EXT_TIMER_INT_ENAB();
}

// Read the current value of the clock, returning the number of hardware
// "ticks" that have occurred (i.e. how far away the current value is from
// the start)

void hal_clock_read(cyg_uint32 *pvalue)
{
    cyg_uint8  cnt0, cnt1, cnt2, cnt3;
    cyg_uint32 timer_val;;

    // first read latches the count
    // Actually, it looks like there is a hardware problem where
    // invalid counts get latched. This do while loop appears
    // to get around the problem.
    do {
	cnt0 = *TIMER_LA0_REG_ADDR & TIMER_COUNT_MASK;
    } while (cnt0 == 0);
    cnt1 = *TIMER_LA1_REG_ADDR & TIMER_COUNT_MASK;
    cnt2 = *TIMER_LA2_REG_ADDR & TIMER_COUNT_MASK;
    cnt3 = *TIMER_LA3_REG_ADDR & 0xf;	/* only 4 bits in most sig. */

    /* now build up the count value */
    timer_val  =  ((cnt0 & 0x40) >> 1) | (cnt0 & 0x1f);
    timer_val |= (((cnt1 & 0x40) >> 1) | (cnt1 & 0x1f)) << 6;
    timer_val |= (((cnt2 & 0x40) >> 1) | (cnt2 & 0x1f)) << 12;
    timer_val |= cnt3 << 18;

    *pvalue = timer_val;
}

// Delay for some usecs.
void hal_delay_us(cyg_uint32 delay)
{
#define _CNT_MASK 0x3fffff
#define _TICKS_PER_USEC (EXT_TIMER_CLK_FREQ / 1000000)
    cyg_uint32 now, last, diff, ticks;

    hal_clock_read(&last);
    diff = ticks = 0;

    while (delay > ticks) {
	hal_clock_read(&now);

	if (now < last)
	    diff += ((_period - last) + now);
	else
	    diff += (now - last);

	last = now;

	if (diff >= _TICKS_PER_USEC) {
	    ticks += (diff / _TICKS_PER_USEC);
	    diff %= _TICKS_PER_USEC;
	}
    }
}

#endif

// -------------------------------------------------------------------------

typedef cyg_uint32 cyg_ISR(cyg_uint32 vector, CYG_ADDRWORD data);

extern void cyg_interrupt_post_dsr( CYG_ADDRWORD intr_obj );

static inline cyg_uint32
hal_call_isr (cyg_uint32 vector)
{
    cyg_ISR *isr;
    CYG_ADDRWORD data;
    cyg_uint32 isr_ret;

    isr = (cyg_ISR*) hal_interrupt_handlers[vector];
    data = hal_interrupt_data[vector];

    isr_ret = (*isr) (vector, data);

#ifdef CYGFUN_HAL_COMMON_KERNEL_SUPPORT
    if (isr_ret & CYG_ISR_CALL_DSR) {
        cyg_interrupt_post_dsr (hal_interrupt_objects[vector]);
    }
#endif

    return isr_ret & ~CYG_ISR_CALL_DSR;
}

void _scrub_ecc(unsigned p)
{
    asm volatile ("ldrb r4, [%0]\n"
		  "strb r4, [%0]\n" : : "r"(p) );
}

static cyg_uint32 nmi_mcu_ISR(cyg_vector_t vector, cyg_addrword_t data)
{
    cyg_uint32 eccr_reg;

    // Read current state of ECC register
    eccr_reg = *ECCR_REG;

    // Turn off all ecc error reporting
    *ECCR_REG = 0x4;

    // Check for ECC Error 0
    if(*MCISR_REG & 0x1) {
	
#ifdef DEBUG_NMI
	diag_printf("ELOG0 = 0x%X\n", *ELOG0_REG);
	diag_printf("ECC Error Detected at Address 0x%X\n",*ECAR0_REG);		
#endif
	
	// Check for single-bit error
        if(!(*ELOG0_REG & 0x00000100)) {
	    // call ECC restoration function
	    _scrub_ecc(*ECAR0_REG);

	    // Clear the MCISR
	    *MCISR_REG = 0x1;
        } else {
#ifdef DEBUG_NMI
            diag_printf("Multi-bit or nibble error\n");
#endif
	}
    }

    // Check for ECC Error 1
    if(*MCISR_REG & 0x2) {

#ifdef DEBUG_NMI
	diag_printf("ELOG0 = 0x%X\n",*ELOG1_REG);
	diag_printf("ECC Error Detected at Address 0x%X\n",*ECAR1_REG);	
#endif
        
	// Check for single-bit error
        if(!(*ELOG1_REG & 0x00000100))  {
	    // call ECC restoration function
	    _scrub_ecc(*ECAR1_REG);
 
	    // Clear the MCISR
	    *MCISR_REG = 0x2;
	}
	else {
#ifdef DEBUG_NMI
            diag_printf("Multi-bit or nibble error\n");
#endif
	}
    }

    // Check for ECC Error N
    if(*MCISR_REG & 0x4) {
	// Clear the MCISR
	*MCISR_REG = 0x4;
	diag_printf("Uncorrectable error during RMW\n");
    }
    
    // Restore ECCR register
    *ECCR_REG = eccr_reg;

    // clear the interrupt condition
    *MCISR_REG = *MCISR_REG & 7;

    return CYG_ISR_HANDLED;
}

static cyg_uint32 nmi_patu_ISR(cyg_vector_t vector, cyg_addrword_t data)
{
    cyg_uint32 status;

    status = *PATUISR_REG;

#ifdef DEBUG_NMI
    if (status & 0x001) diag_printf ("PPCI Master Parity Error\n");
    if (status & 0x002) diag_printf ("PPCI Target Abort (target)\n");
    if (status & 0x004) diag_printf ("PPCI Target Abort (master)\n");
    if (status & 0x008) diag_printf ("PPCI Master Abort\n");
    if (status & 0x010) diag_printf ("Primary P_SERR# Detected\n");
    if (status & 0x080) diag_printf ("Internal Bus Master Abort\n");
    if (status & 0x100) diag_printf ("PATU BIST Interrupt\n");
    if (status & 0x200) diag_printf ("PPCI Parity Error Detected\n");
    if (status & 0x400) diag_printf ("Primary P_SERR# Asserted\n");
#endif

    *PATUISR_REG = status & 0x79f;
    *PATUSR_REG |= 0xf900;

    return CYG_ISR_HANDLED;
}


static cyg_uint32 nmi_satu_ISR(cyg_vector_t vector, cyg_addrword_t data)
{
    cyg_uint32 status;

    status = *SATUISR_REG;

#ifdef DEBUG_NMI
    if (status & 0x001) diag_printf ("SPCI Master Parity Error\n");
    if (status & 0x002) diag_printf ("SPCI Target Abort (target)\n");
    if (status & 0x004) diag_printf ("SPCI Target Abort (master)\n");
    if (status & 0x008) diag_printf ("SPCI Master Abort\n");
    if (status & 0x010) diag_printf ("Secondary P_SERR# Detected\n");
    if (status & 0x080) diag_printf ("Internal Bus Master Abort\n");
    if (status & 0x200) diag_printf ("SPCI Parity Error Detected\n");
    if (status & 0x400) diag_printf ("Secondary P_SERR# Asserted\n");
#endif

    *SATUISR_REG = status & 0x69f;
    *SATUSR_REG |= 0xf900;

    return CYG_ISR_HANDLED;
}

static cyg_uint32 nmi_pb_ISR(cyg_vector_t vector, cyg_addrword_t data)
{
    cyg_uint32 status;

    status = *PBISR_REG;

#ifdef DEBUG_NMI
    if (status & 0x001) diag_printf ("PPCI Master Parity Error\n");
    if (status & 0x002) diag_printf ("PPCI Target Abort (target)\n");
    if (status & 0x004) diag_printf ("PPCI Target Abort (master)\n");
    if (status & 0x008) diag_printf ("PPCI Master Abort\n");
    if (status & 0x010) diag_printf ("Primary P_SERR# Asserted\n");
    if (status & 0x020) diag_printf ("PPCI Parity Error Detected\n");
#endif

    *PBISR_REG = status & 0x3f;
    *PSR_REG |= 0xf900;

    return CYG_ISR_HANDLED;
}


static cyg_uint32 nmi_sb_ISR(cyg_vector_t vector, cyg_addrword_t data)
{
    cyg_uint32 status;

    status = *SBISR_REG;

    *SBISR_REG = status & 0x7f;
    *SSR_REG |= 0xf900;

    return CYG_ISR_HANDLED;
}


static cyg_uint32 nfiq_ISR(cyg_vector_t vector, cyg_addrword_t data)
{
    cyg_uint32 sources;
    int i, isr_ret;

    // Check NMI
    sources = *NISR_REG;
    for (i = 0; i < 12; i++) {
	if (sources & (1<<i)) {
	    isr_ret = hal_call_isr (CYGNUM_HAL_INTERRUPT_MCU_ERR + i);
	    CYG_ASSERT (isr_ret & CYG_ISR_HANDLED, "Interrupt not handled");
	    return isr_ret;
	}
    }
    return 0;
}

static cyg_uint32 nirq_ISR(cyg_vector_t vector, cyg_addrword_t data)
{
    cyg_uint32 sources;
    int i, isr_ret;
    cyg_uint32 xint3_isr, xint3_mask;

    // Check XINT3
    sources = (xint3_isr = *X3ISR_REG) & ~(xint3_mask = *X3MASK_REG);
    for (i = 0; i <= CYGNUM_HAL_INTERRUPT_XINT3_BITS; i++) {
	if (sources & (1 << i)) {
	    isr_ret = hal_call_isr (CYGNUM_HAL_INTERRUPT_XINT3_BIT0 + i);
            if ((isr_ret & CYG_ISR_HANDLED) == 0) {
                diag_printf("XINT3 int not handled - ISR: %02x, MASK: %02x\n", xint3_isr, ~xint3_mask);
            }
	    CYG_ASSERT (isr_ret & CYG_ISR_HANDLED, "XINT3 Interrupt not handled");
	    return isr_ret;
	}
    }
    // What to do about S_INTA-S_INTC?

    // Check XINT6
    sources = *X6ISR_REG;
    for (i = 0; i < 3; i++) {
	// check DMA irqs
	if (sources & (1<<i)) {
	    isr_ret = hal_call_isr (CYGNUM_HAL_INTERRUPT_DMA_0 + i);
	    CYG_ASSERT (isr_ret & CYG_ISR_HANDLED, "DMA Interrupt not handled");
	    return isr_ret;
	}
    }
    if (sources & 0x10) {
	// performance monitor
	_80312_EMISR = *EMISR_REG;
	if (_80312_EMISR & 1) {
	    isr_ret = hal_call_isr (CYGNUM_HAL_INTERRUPT_GTSC);
	    CYG_ASSERT (isr_ret & CYG_ISR_HANDLED, "GTSC Interrupt not handled");
	}
	if (_80312_EMISR & 0x7ffe) {
	    isr_ret = hal_call_isr (CYGNUM_HAL_INTERRUPT_PEC);
	    CYG_ASSERT (isr_ret & CYG_ISR_HANDLED, "PEC Interrupt not handled");
	}
	return 0;
    }
    if (sources & 0x20) {
	// Application Accelerator Unit
	isr_ret = hal_call_isr (CYGNUM_HAL_INTERRUPT_AAIP);
	CYG_ASSERT (isr_ret & CYG_ISR_HANDLED, "AAIP Interrupt not handled");
	return isr_ret;
    }
    
    // Check XINT7
    sources = *X7ISR_REG;
    if (sources & 2) {
	// I2C Unit
	cyg_uint32 i2c_sources = *ISR_REG;