hal_iop310.h

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#ifndef CYGONCE_HAL_IOP310_H
#define CYGONCE_HAL_IOP310_H

/*=============================================================================
//
//      hal_iop310.h
//
//      HAL Description of IOP310 (IQ80200/IQ80310) control registers, etc.
//
//=============================================================================
//####ECOSGPLCOPYRIGHTBEGIN####
// -------------------------------------------
// This file is part of eCos, the Embedded Configurable Operating System.
// Copyright (C) 1998, 1999, 2000, 2001, 2002, 2003 Red Hat, Inc.
// Copyright (C) 2002 Gary Thomas
//
// eCos is free software; you can redistribute it and/or modify it under
// the terms of the GNU General Public License as published by the Free
// Software Foundation; either version 2 or (at your option) any later version.
//
// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or
// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
// for more details.
//
// You should have received a copy of the GNU General Public License along
// with eCos; if not, write to the Free Software Foundation, Inc.,
// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
//
// As a special exception, if other files instantiate templates or use macros
// or inline functions from this file, or you compile this file and link it
// with other works to produce a work based on this file, this file does not
// by itself cause the resulting work to be covered by the GNU General Public
// License. However the source code for this file must still be made available
// in accordance with section (3) of the GNU General Public License.
//
// This exception does not invalidate any other reasons why a work based on
// this file might be covered by the GNU General Public License.
//
// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
// at http://sources.redhat.com/ecos/ecos-license/
// -------------------------------------------
//####ECOSGPLCOPYRIGHTEND####
//=============================================================================
//#####DESCRIPTIONBEGIN####
//
// Author(s):    msalter
// Contributors: msalter, gthomas
// Date:         2000-10-10
// Purpose:      Intel IOP310 hardware description
// Description:
// Usage:        #include <cyg/hal/hal_iop310.h>
//
//####DESCRIPTIONEND####
//
//===========================================================================*/

#include <cyg/hal/hal_xscale.h>

#ifndef __ASSEMBLER__
// Platform specific initializations
extern void hal_plf_hardware_init(void);
#endif

// Serial ports
#define IOP310_SERIAL_PORT_A 0xFE800000
#define IOP310_SERIAL_PORT_B 0xFE810000

#define DCACHE_FLUSH_AREA 0xc0000000

// Addresses of the left and right 7-segment display
#define DISPLAY_LEFT    0xFE840000
#define DISPLAY_RIGHT   0xFE850000

// 7-segment encodings for the hex display
#define DISPLAY_0       0xc0
#define DISPLAY_1       0xf9
#define DISPLAY_2       0xa4
#define DISPLAY_3       0xb0
#define DISPLAY_4       0x99
#define DISPLAY_5       0x92
#define DISPLAY_6       0x82
#define DISPLAY_7       0xF8
#define DISPLAY_8       0x80
#define DISPLAY_9       0x90
#define DISPLAY_A       0x88
#define DISPLAY_B       0x83
#define DISPLAY_C       0xa7
#define DISPLAY_D       0xa1
#define DISPLAY_E       0x86
#define DISPLAY_F       0x8e

#ifndef iop310_is_host
/* Backplane Detect Register */
#define BACKPLANE_DET_REG       ((volatile unsigned char *)0xfe870000)
#  define BP_HOST_BIT           0x1
#define iop310_is_host()        (*BACKPLANE_DET_REG & BP_HOST_BIT)
#endif

// XINT3 mask register
#define X3ISR_REG   ((volatile unsigned char *)0xfe820000)
#define X3MASK_REG  ((volatile unsigned char *)0xfe860000)
#  define XINT3_TIMER    0x01
#  define XINT3_ETHERNET 0x02
#  define XINT3_UART_1   0x04
#  define XINT3_UART_2   0x08
#  define XINT3_PCI_INTD 0x10

/* PAL-based external timer definitions */
#define TIMER_LA0_REG_ADDR      ((volatile unsigned char *)0xfe880000)
#define TIMER_LA1_REG_ADDR      ((volatile unsigned char *)0xfe890000)
#define TIMER_LA2_REG_ADDR      ((volatile unsigned char *)0xfe8a0000)
#define TIMER_LA3_REG_ADDR      ((volatile unsigned char *)0xfe8b0000)
#define TIMER_ENABLE_REG_ADDR   ((volatile unsigned char *)0xfe8c0000)

#define TIMER_COUNT_MASK                0x5f    /* 6 bits of timer data with the MSB in bit 6 not bit 5 */
#define TIMER_CNT_ENAB                  0x1
#define TIMER_INT_ENAB                  0x2
#define EXT_TIMER_CLK_FREQ              33000000        /* external timer runs at 33 MHz */
#define TICKS_10MSEC                    100                     /* 10msec = 100 ticks/sec */
#define EXT_TIMER_10MSEC_COUNT  (EXT_TIMER_CLK_FREQ / TICKS_10MSEC)
#define TICKS_5MSEC                             200                     /* 5msec = 200 ticks/sec */
#define EXT_TIMER_5MSEC_COUNT   (EXT_TIMER_CLK_FREQ / TICKS_5MSEC)

#define EXT_TIMER_CNT_ENAB()            (*TIMER_ENABLE_REG_ADDR |= TIMER_CNT_ENAB)
#define EXT_TIMER_CNT_DISAB()           (*TIMER_ENABLE_REG_ADDR &= ~TIMER_CNT_ENAB)
#define EXT_TIMER_INT_ENAB()            (*TIMER_ENABLE_REG_ADDR |= TIMER_INT_ENAB)
#define EXT_TIMER_INT_DISAB()           (*TIMER_ENABLE_REG_ADDR &= ~TIMER_INT_ENAB)

// Companion chip MCU registers
#define    MMR_BASE         0x00001500
#define    SDIR_OFF         0x00000000
#define    SDCR_OFF         0x00000004
#define    SDBR_OFF         0x00000008
#define    SBR0_OFF         0x0000000C
#define    SBR1_OFF         0x00000010
#define    ECCR_OFF         0x00000034
#define    FEBR1_OFF        0x00000050
#define    FBSR1_OFF        0x00000058
#define    FWSR0_OFF        0x0000005C
#define    FWSR1_OFF        0x00000060
#define    RFR_OFF          0x00000068

// MCU Register Values
#define    MRS_CAS_LAT_2    0x00000000
#define    MRS_CAS_LAT_3    0x00000001
#define    MRS_PRECHRG      0x00000002       
#define    MRS_NO_OP        0x00000003
#define    MRS_AUTO_RFRSH   0x00000004
#define    MRS_NORM_OP      0x00000006
#define    MRS_NOP_DELAY    0x00004000
#define    SDCR_INIT_VAL    0x00000aa0  // was 0x14
#define    SBR0_INIT_VAL    0x00000008  // 32 Meg Boundary (64 mbit device)
#define    SBR1_INIT_VAL    0x00000008  // 32 Meg Boundary (64 mbit device)
#define    ECCR_INIT_VAL    0x0000000C  // ECC enabled, correction on and no reporting
#define    RFR_INIT_VAL     0x00000600  // Initial Refresh Rate
#define    FBSR1_INIT_VAL   0x00000040  // 8MB Bank Size
#define    FWSR0_INIT_VAL   0x00000001  // 1ws add-data (needed for PP state machine), 0ws recovery
#define    FWSR1_INIT_VAL   0x00000000  // 0ws add-data, 0ws recovery


/**************************
 * I2C Bus Interface Unit *
 **************************/

/* Processor I2C Device ID */
#define I2C_DEVID       0x02  /* I2C slave address to which the unit responds when in slave-receive mode */

/* Timeout limit for SDRAM EEPROM to respond */
#define I2C_TIMOUT      0x1000000  /* bumped this way up...used to be 0x100000*/ 

/* Control Register */
#define ICR_ADDR        0x00001680  /* Address */
#define ICR_START       0x0001  /* 1:send a Start condition to the I2C when in master mode */
#define ICR_STOP        0x0002  /* 1:send a Stop condition after next data byte transferred on I2C bus in master mode */
#define ICR_ACK         0x0004  /* Ack/Nack control: 1:Nack, 0:Ack (negative or positive pulse) */
#define ICR_TRANSFER    0x0008  /* 1:send/receive byte, 0:cleared by I2C unit when done */
#define ICR_ABORT       0x0010  /* 1:I2C sends STOP w/out data permission, 0:ICR bit used only */
#define ICR_SCLENB      0x0020  /* I2C clock output: 1:Enabled, 0:Disabled. ICCR configured before ! */
#define ICR_ENB         0x0040  /* I2C unit: 1:Enabled, 0:Disabled */
#define ICR_GCALL       0x0080  /* General Call: 1:Disabled, 0:Enabled */
#define ICR_IEMPTY      0x0100  /* 1: IDBR Transmit Empty Interrupt Enable */
#define ICR_IFULL       0x0200  /* 1: IDBR Receive Full Interrupt Enable */
#define ICR_IERR        0x0400  /* 1: Bus Error Interrupt Enable */
#define ICR_ISTOP       0x0800  /* 1: Slave Stop Detected Interrupt Enable */
#define ICR_IARB        0x1000  /* 1: Arbitration Loss Detected Interrupt Enable */
#define ICR_ISADDR      0x2000  /* 1: Slave Address Detected Interrupt Enable */
#define ICR_RESET       0x4000  /* 1: I2C unit reset */

/* Status Register */
#define ISR_ADDR        0x00001684  /* Address */
#define ISR_RWMODE      0x0001  /* 1: I2C in master receive = slave transmit mode */
#define ISR_ACK         0x0002  /* 1: I2C received/sent a Nack, 0: Ack */
#define ISR_BUSY        0x0004  /* 1: Processor's I2C unit busy */
#define ISR_BUSBUSY     0x0008  /* 1: I2C bus busy. Processor's I2C unit not involved */
#define ISR_STOP        0x0010  /* 1: Slave Stop detected (when in slave mode: receive or transmit) */
#define ISR_ARB         0x0020  /* 1: Arbitration Loss Detected */
#define ISR_EMPTY       0x0040  /* 1: Transfer finished on I2C bus. If enabled in ICR, interrupt signaled */
#define ISR_FULL        0x0080  /* 1: IDBR received new byte from I2C bus. If ICR, interrupt signaled */
#define ISR_GCALL       0x0100  /* 1: I2C unit received a General Call address */
#define ISR_SADDR       0x0200  /* 1: I2C unit detected a 7-bit address matching the general call or ISAR */
#define ISR_ERROR       0x0400  /* Bit set by unit when a Bus Error detected */

#define ISAR_ADDR       0x00001688  /* Address of the I2C Slave Address Register */
#define IDBR_ADDR       0x0000168C  /* Address of the I2C Data Buffer Register */
#define IDBR_MASK       0x000000ff
#define IDBR_MODE       0x01
#define ICCR_ADDR       0x00001690  /* Address of the I2C Clock Control Register */
#define IBMR_ADDR       0x00001694  /* Address of the I2C Bus Monitor Register */

/* SDRAM configuration */

/* SDRAM bank size values (SPD << 2) */
#define         RAM_0MEG        
#define         RAM_4MEG        4
#define         RAM_8MEG        8
#define         RAM_16MEG       16
#define         RAM_32MEG       32
#define         RAM_64MEG       64
#define         RAM_128MEG      128
#define         RAM_256MEG      256

/* SBR register definitions (valid bits are [7:3])*/
#define         SBR_32MEG       0x08
#define         SBR_64MEG       0x10
#define         SBR_128MEG      0x20
#define         SBR_256MEG      0x40

/* Drive Strengths - assume single DIMM configuration */
#define    SDCR_1BANK_X16       0x0aa0
#define    SDCR_2BANK_X16       0x12c8
#define    SDCR_1BANK_X8        0x1520
#define    SDCR_2BANK_X8        0x1548

/* SDRAM PD bytes                               */
#define         BANKCNT_BYTE     0x06 /* Byte #5 of SPD: number of module banks */
#define         SDRAM_WIDTH_BYTE 0x0e /* Byte #13 of SPD: DRAM width */
#define         BANKSZ_BYTE      0x20 /* Byte #31 of SPD: module bank density */
#define         CHECKSUM_BYTE    0x40 /* Byte #63 of SPD: checksum for bytes 0-62 */
#define         CONFIG_BYTE     0x0C  /* Byte #11 of SPD: DIMM configuration type (Parity or not, EEC) */

#define SDRAM_DEVID     0xA2  /* SDRAM Device ID  */

// Yavapai PCI and Peripheral Interrupt Unit
/*** Yavapai Registers ***/

/* PCI-to-PCI Bridge Unit 0000 1000H through 0000 10FFH */
#define VIDR_ADDR       0x00001000
#define DIDR_ADDR       0x00001002
#define PCR_ADDR        0x00001004
#define PSR_ADDR        0x00001006
#define RIDR_ADDR       0x00001008
#define CCR_ADDR        0x00001009
#define CLSR_ADDR       0x0000100C
#define PLTR_ADDR       0x0000100D
#define HTR_ADDR        0x0000100E
/* Reserved 0x0000100F through  0x00001017 */
#define PBNR_ADDR       0x00001018
#define SBNR_ADDR       0x00001019
#define SUBBNR_ADDR     0x0000101A
#define SLTR_ADDR       0x0000101B
#define IOBR_ADDR       0x0000101C
#define IOLR_ADDR       0x0000101D
#define SSR_ADDR        0x0000101E
#define MBR_ADDR        0x00001020
#define MLR_ADDR        0x00001022
#define PMBR_ADDR       0x00001024
#define PMLR_ADDR       0x00001026
/* Reserved 0x00001028 through 0x00001033 */
#define BSVIR_ADDR      0x00001034
#define BSIR_ADDR       0x00001036
/* Reserved 0x00001038 through 0x0000103D */
#define BCR_ADDR        0x0000103E
#define EBCR_ADDR       0x00001040
#define SISR_ADDR       0x00001042
#define PBISR_ADDR      0x00001044
#define SBISR_ADDR      0x00001048
#define SACR_ADDR       0x0000104C
#define PIRSR_ADDR      0x00001050
#define SIOBR_ADDR      0x00001054
#define SIOLR_ADDR      0x00001055
#define SCCR_ADDR       0x00001056              /* EAS inconsistent */
#define SMBR_ADDR       0x00001058
#define SMLR_ADDR       0x0000105A
#define SDER_ADDR       0x0000105C
#define QCR_ADDR        0x0000105E
#define CDTR_ADDR       0x00001060              /* EAS inconsistent */
/* Reserved 0x00001064 through 0x000010FFH */

/* Performance Monitoring Unit 0000 1100H through 0000 11FFH */
#define GTMR_ADDR       0x00001100
#define ESR_ADDR        0x00001104
#define EMISR_ADDR      0x00001108
/* Reserved 0x0000110C */                       /* EAS inconsistent */
#define GTSR_ADDR       0x00001110              /* EAS inconsistent */
#define PECR1_ADDR      0x00001114              /* EAS inconsistent */
#define PECR2_ADDR      0x00001118              /* EAS inconsistent */
#define PECR3_ADDR      0x0000111C              /* EAS inconsistent */
#define PECR4_ADDR      0x00001120              /* EAS inconsistent */
#define PECR5_ADDR      0x00001124              /* EAS inconsistent */
#define PECR6_ADDR      0x00001128              /* EAS inconsistent */
#define PECR7_ADDR      0x0000112C              /* EAS inconsistent */
#define PECR8_ADDR      0x00001130              /* EAS inconsistent */
#define PECR9_ADDR      0x00001134              /* EAS inconsistent */
#define PECR10_ADDR     0x00001138              /* EAS inconsistent */
#define PECR11_ADDR     0x0000113C              /* EAS inconsistent */
#define PECR12_ADDR     0x00001140              /* EAS inconsistent */
#define PECR13_ADDR     0x00001144              /* EAS inconsistent */
#define PECR14_ADDR     0x00001148              /* EAS inconsistent */
/* Reserved 0x0000104C through 0x000011FFH */   /* EAS inconsistent */

/* Address Translation Unit 0000 1200H through 0000 12FFH */
#define ATUVID_ADDR             0x00001200
#define ATUDID_ADDR             0x00001202
#define PATUCMD_ADDR            0x00001204
#define PATUSR_ADDR             0x00001206
#define ATURID_ADDR             0x00001208
#define ATUCCR_ADDR             0x00001209
#define ATUCLSR_ADDR            0x0000120C
#define ATULT_ADDR              0x0000120D
#define ATUHTR_ADDR             0x0000120E
#define ATUBISTR_ADDR           0x0000120F
#define PIABAR_ADDR             0x00001210
/* Reserved 0x00001214 through 0x0000122B */
#define ASVIR_ADDR              0x0000122C
#define ASIR_ADDR               0x0000122E
#define ERBAR_ADDR              0x00001230
/* Reserved 0x00001234 */
/* Reserved 0x00001238 */
#define ATUILR_ADDR             0x0000123C
#define ATUIPR_ADDR             0x0000123D
#define ATUMGNT_ADDR            0x0000123E
#define ATUMLAT_ADDR            0x0000123F
#define PIALR_ADDR              0x00001240
#define PIATVR_ADDR             0x00001244
#define SIABAR_ADDR             0x00001248
#define SIALR_ADDR              0x0000124C
#define SIATVR_ADDR             0x00001250
#define POMWVR_ADDR             0x00001254