hal_verde.h

eCos操作系统源码

#define SDIR_CMD_ENABLE_DLL     0x00000006
#define SDIR_CMD_CAS_LAT_2_A    0x00000002
#define SDIR_CMD_CAS_LAT_2_B    0x00000000
#define SDIR_CMD_AUTO_REFRESH   0x00000007


// --------------------------------------------------------------------------
// Peripheral Bus Interface Unit  (Chapter 8)
#define PBIU_PBCR	REG32(0,0xffffe680)
#define PBIU_PBSR	REG32(0,0xffffe684)
#define PBIU_PBAR0	REG32(0,0xffffe688)
#define PBIU_PBLR0	REG32(0,0xffffe68c)
#define PBIU_PBAR1	REG32(0,0xffffe690)
#define PBIU_PBLR1	REG32(0,0xffffe694)
#define PBIU_PBAR2	REG32(0,0xffffe698)
#define PBIU_PBLR2	REG32(0,0xffffe69c)
#define PBIU_PBAR3	REG32(0,0xffffe6a0)
#define PBIU_PBLR3	REG32(0,0xffffe6a4)
#define PBIU_PBAR4	REG32(0,0xffffe6a8)
#define PBIU_PBLR4	REG32(0,0xffffe6ac)
#define PBIU_PBAR5	REG32(0,0xffffe6b0)
#define PBIU_PBLR5	REG32(0,0xffffe6b4)
#define PBIU_PBVR0	REG32(0,0xffffe6c0)
#define PBIU_PBVR1	REG32(0,0xffffe6c4)
#define PBIU_PBVR2	REG32(0,0xffffe6c8)
#define PBIU_PBVR3	REG32(0,0xffffe6cc)
#define PBIU_PBVR4	REG32(0,0xffffe6d0)
#define PBIU_PBVR5	REG32(0,0xffffe6d8)
#define PBIU_PBVR6	REG32(0,0xffffe6dc)

#define PBCR_ENABLE     1

#define PBCR_ERR_VALID    0x01
#define PBCR_ERR_WRITE    0x02
#define PBCR_ERR_TYPEMASK 0x0C

#define PBAR_FLASH      0x200
#define PBAR_RCWAIT_1   0x000
#define PBAR_RCWAIT_4   0x040
#define PBAR_RCWAIT_8   0x080
#define PBAR_RCWAIT_12  0x0C0
#define PBAR_RCWAIT_16  0x100
#define PBAR_RCWAIT_20  0x1C0
#define PBAR_ADWAIT_4   0x000
#define PBAR_ADWAIT_8   0x004
#define PBAR_ADWAIT_12  0x008
#define PBAR_ADWAIT_16  0x00C
#define PBAR_ADWAIT_20  0x01C
#define PBAR_BUS_8      0x000
#define PBAR_BUS_16     0x001
#define PBAR_BUS_32     0x002

#define PBLR_SZ_4K      0xfffff000
#define PBLR_SZ_8K      0xffffe000
#define PBLR_SZ_16K     0xffffc000
#define PBLR_SZ_32K     0xffff8000
#define PBLR_SZ_64K     0xffff0000
#define PBLR_SZ_128K    0xfffe0000
#define PBLR_SZ_256K    0xfffc0000
#define PBLR_SZ_512K    0xfff80000
#define PBLR_SZ_1M      0xfff00000
#define PBLR_SZ_2M      0xffe00000
#define PBLR_SZ_4M      0xffc00000
#define PBLR_SZ_8M      0xff800000
#define PBLR_SZ_16M     0xff000000
#define PBLR_SZ_32M     0xfe000000
#define PBLR_SZ_64M     0xfc000000
#define PBLR_SZ_128M    0xf8000000
#define PBLR_SZ_256M    0xf0000000
#define PBLR_SZ_512M    0xe0000000
#define PBLR_SZ_1G      0xc0000000
#define PBLR_SZ_2G      0x80000000
#define PBLR_SZ_DISABLE 0x00000000

// --------------------------------------------------------------------------
// I2C (Chapter 9)
#define I2C_BASE0       0xfffff680
#define I2C_BASE1       0xfffff6A0

#define I2C_ICR	        0x00
#define I2C_ISR	        0x04
#define I2C_ISAR	0x08
#define I2C_IDBR	0x0c
#define I2C_IBMR	0x14

#define I2C_ICR0	REG32(I2C_BASE0,I2C_ICR)
#define I2C_ICR1	REG32(I2C_BASE1,I2C_ICR)
#define I2C_ISR0	REG32(I2C_BASE0,I2C_ISR)
#define I2C_ISR1	REG32(I2C_BASE1,I2C_ISR)
#define I2C_ISAR0	REG32(I2C_BASE0,I2C_ISAR)
#define I2C_ISAR1	REG32(I2C_BASE1,I2C_ISAR)
#define I2C_IDBR0	REG32(I2C_BASE0,I2C_IDBR)
#define I2C_IDBR1	REG32(I2C_BASE1,I2C_IDBR)
#define I2C_IBMR0	REG32(I2C_BASE0,I2C_IBMR)
#define I2C_IBMR1	REG32(I2C_BASE1,I2C_IBMR)

// Control Register bits
#define	ICR_START	0x0001  /* 1:send a Start condition to the I2C when in master mode */
#define	ICR_STOP	0x0002  /* 1:send a Stop condition after next byte transferred in master mode */
#define	ICR_ACK		0x0004  /* Ack/Nack control: 1:Nack, 0:Ack (negative or positive pulse) */
#define	ICR_TRANSFER	0x0008  /* 1:send/receive byte, 0:cleared by I2C unit when done */
#define	ICR_ABORT	0x0010  /* 1:I2C sends STOP w/out data permission, 0:ICR bit used only */
#define	ICR_SCLENB	0x0020  /* I2C clock output: 1:Enabled, 0:Disabled. ICCR configured before ! */
#define	ICR_ENB		0x0040  /* I2C unit: 1:Enabled, 0:Disabled */
#define	ICR_GCALL	0x0080  /* General Call: 1:Disabled, 0:Enabled */
#define	ICR_IEMPTY	0x0100  /* 1: IDBR Transmit Empty Interrupt Enable */
#define	ICR_IFULL	0x0200  /* 1: IDBR Receive Full Interrupt Enable */
#define	ICR_IERR	0x0400  /* 1: Bus Error Interrupt Enable */
#define	ICR_ISTOP	0x0800  /* 1: Slave Stop Detected Interrupt Enable */
#define	ICR_IARB	0x1000  /* 1: Arbitration Loss Detected Interrupt Enable */
#define	ICR_ISADDR	0x2000  /* 1: Slave Address Detected Interrupt Enable */
#define	ICR_RESET	0x4000  /* 1: I2C unit reset */

// Status Register bits
#define	ISR_RWMODE	0x0001  /* 1: I2C in master receive = slave transmit mode */
#define	ISR_ACK		0x0002  /* 1: I2C received/sent a Nack, 0: Ack */
#define	ISR_BUSY	0x0004  /* 1: Processor's I2C unit busy */
#define	ISR_BUSBUSY	0x0008  /* 1: I2C bus busy. Processor's I2C unit not involved */
#define	ISR_STOP	0x0010  /* 1: Slave Stop detected (when in slave mode: receive or transmit) */
#define	ISR_ARB		0x0020  /* 1: Arbitration Loss Detected */
#define	ISR_EMPTY	0x0040  /* 1: Transfer finished on I2C bus. If enabled in ICR, interrupt signaled */
#define	ISR_FULL	0x0080  /* 1: IDBR received new byte from I2C bus. If ICR, interrupt signaled */
#define	ISR_GCALL	0x0100  /* 1: I2C unit received a General Call address */
#define	ISR_SADDR	0x0200  /* 1: I2C unit detected a 7-bit address matching the general call or ISAR */
#define	ISR_ERROR	0x0400  /* Bit set by unit when a Bus Error detected */

#define	IDBR_MASK	0x000000ff
#define	IDBR_MODE	0x01

// --------------------------------------------------------------------------
// Arbitration (Chapter 11)
#define ARB_IACR        REG32(0,0xffffe780)
#define ARB_MTTR1       REG32(0,0xffffe784)
#define ARB_MTTR2       REG32(0,0xffffe788)

#define IACR_PRI_HIGH    0
#define IACR_PRI_MED     1
#define IACR_PRI_LOW     2
#define IACR_PRI_OFF     3

// macros to set priority for various units
#define IACR_ATU(x)      ((x) << 0)
#define IACR_DMA0(x)     ((x) << 4)
#define IACR_DMA1(x)     ((x) << 6)
#define IACR_CORE(x)     ((x) << 10)
#define IACR_AAU(x)      ((x) << 12)
#define IACR_PBI(x)      ((x) << 14)


// --------------------------------------------------------------------------
// Timers (Chapter 14)
#define TU_TMR0	    REG32(0,0xffffe7e0)
#define TU_TMR1	    REG32(0,0xffffe7e4)
#define TU_TCR0	    REG32(0,0xffffe7e8)
#define TU_TCR1	    REG32(0,0xffffe7ec)
#define TU_TRR0	    REG32(0,0xffffe7f0)
#define TU_TRR1	    REG32(0,0xffffe7f4)
#define TU_TISR	    REG32(0,0xffffe7f8)
#define TU_WDTCR    REG32(0,0xffffe7fc)

#define TMR_TC      0x01  // terminal count
#define TMR_ENABLE  0x02  // timer enable
#define TMR_RELOAD  0x04  // auto reload enable
#define TMR_CLK_1   0x00  // CCLK (core clock)
#define TMR_CLK_4   0x10  // CCLK/4
#define TMR_CLK_8   0x20  // CCLK/8
#define TMR_CLK_16  0x30  // CCLK/16

#ifndef __ASSEMBLER__
// For full read/write access, you have to use coprocessor insns.
#define TMR0_READ(val)    asm volatile ("mrc p6, 0, %0, c0, c1, 0" : "=r" (val))
#define _TMR0_WRITE(val)  asm volatile ("mcr p6, 0, %0, c0, c1, 0" : : "r" (val))
#define TMR1_READ(val)    asm volatile ("mrc p6, 0, %0, c1, c1, 0" : "=r" (val))
#define _TMR1_WRITE(val)  asm volatile ("mcr p6, 0, %0, c1, c1, 0" : : "r" (val))
#define TCR0_READ(val)    asm volatile ("mrc p6, 0, %0, c2, c1, 0" : "=r" (val))
#define _TCR0_WRITE(val)  asm volatile ("mcr p6, 0, %0, c2, c1, 0" : : "r" (val))
#define TCR1_READ(val)    asm volatile ("mrc p6, 0, %0, c3, c1, 0" : "=r" (val))
#define _TCR1_WRITE(val)  asm volatile ("mcr p6, 0, %0, c3, c1, 0" : : "r" (val))
#define TRR0_READ(val)    asm volatile ("mrc p6, 0, %0, c4, c1, 0" : "=r" (val))
#define _TRR0_WRITE(val)  asm volatile ("mcr p6, 0, %0, c4, c1, 0" : : "r" (val))
#define TRR1_READ(val)    asm volatile ("mrc p6, 0, %0, c5, c1, 0" : "=r" (val))
#define _TRR1_WRITE(val)  asm volatile ("mcr p6, 0, %0, c5, c1, 0" : : "r" (val))
#define TISR_READ(val)    asm volatile ("mrc p6, 0, %0, c6, c1, 0" : "=r" (val))
#define _TISR_WRITE(val)  asm volatile ("mcr p6, 0, %0, c6, c1, 0" : : "r" (val))
#define _WDTCR_READ(val)  asm volatile ("mrc p6, 0, %0, c7, c1, 0" : "=r" (val))
#define _WDTCR_WRITE(val) asm volatile ("mcr p6, 0, %0, c7, c1, 0" : : "r" (val))

static inline void TMR0_WRITE(cyg_uint32 val) { _TMR0_WRITE(val); }
static inline void TMR1_WRITE(cyg_uint32 val) { _TMR1_WRITE(val); }
static inline void TCR0_WRITE(cyg_uint32 val) { _TCR0_WRITE(val); }
static inline void TCR1_WRITE(cyg_uint32 val) { _TCR1_WRITE(val); }
static inline void TRR0_WRITE(cyg_uint32 val) { _TRR0_WRITE(val); }
static inline void TRR1_WRITE(cyg_uint32 val) { _TRR1_WRITE(val); }
static inline void TISR_WRITE(cyg_uint32 val) { _TISR_WRITE(val); }
#endif

// --------------------------------------------------------------------------
// Interrupts (Chapter 15)
#define INTCTL	REG32(0,0xffffe7d0)
#define INTSTR	REG32(0,0xffffe7d4)
#define IINTSRC	REG32(0,0xffffe7d8)
#define FINTSRC	REG32(0,0xffffe7dc)
#define PIRSR	REG32(0,0xffffe1ec)

#ifndef __ASSEMBLER__
#define INTCTL_READ(val)   asm volatile ("mrc p6, 0, %0, c0, c0, 0" : "=r" (val))
#define _INTCTL_WRITE(val) asm volatile ("mcr p6, 0, %0, c0, c0, 0" : : "r" (val))
#define INTSTR_READ(val)   asm volatile ("mrc p6, 0, %0, c4, c0, 0" : "=r" (val))
#define _INTSTR_WRITE(val) asm volatile ("mcr p6, 0, %0, c4, c0, 0" : : "r" (val))
#define IINTSRC_READ(val)  asm volatile ("mrc p6, 0, %0, c8, c0, 0" : "=r" (val))
#define FINTSRC_READ(val)  asm volatile ("mrc p6, 0, %0, c9, c0, 0" : "=r" (val))

static inline void INTCTL_WRITE(cyg_uint32 val) { _INTCTL_WRITE(val); }
static inline void INTSTR_WRITE(cyg_uint32 val) { _INTSTR_WRITE(val); }
#endif

// --------------------------------------------------------------------------
// GPIO (Chapter 15)
#define GPIO_GPOE	REG8(0,0xffffe7c4)
#define GPIO_GPID	REG8(0,0xffffe7c8)
#define GPIO_GPOD	REG8(0,0xffffe7cc)

#endif // CYGONCE_HAL_ARM_XSCALE_HAL_VERDE_H
// EOF hal_verde.h