📄 hal_verde.h
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/*=============================================================================//// hal_verde.h//// Verde I/O Coprocessor support (register layout, etc)////=============================================================================//####ECOSGPLCOPYRIGHTBEGIN####// -------------------------------------------// This file is part of eCos, the Embedded Configurable Operating System.// Copyright (C) 1998, 1999, 2000, 2001, 2002, 2003 Red Hat, Inc.//// eCos is free software; you can redistribute it and/or modify it under// the terms of the GNU General Public License as published by the Free// Software Foundation; either version 2 or (at your option) any later version.//// eCos is distributed in the hope that it will be useful, but WITHOUT ANY// WARRANTY; without even the implied warranty of MERCHANTABILITY or// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License// for more details.//// You should have received a copy of the GNU General Public License along// with eCos; if not, write to the Free Software Foundation, Inc.,// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.//// As a special exception, if other files instantiate templates or use macros// or inline functions from this file, or you compile this file and link it// with other works to produce a work based on this file, this file does not// by itself cause the resulting work to be covered by the GNU General Public// License. However the source code for this file must still be made available// in accordance with section (3) of the GNU General Public License.//// This exception does not invalidate any other reasons why a work based on// this file might be covered by the GNU General Public License.//// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.// at http://sources.redhat.com/ecos/ecos-license/// -------------------------------------------//####ECOSGPLCOPYRIGHTEND####//=============================================================================//#####DESCRIPTIONBEGIN####//// Author(s): msalter// Contributors: msalter// Date: 2001-12-03// Purpose: // Description: Verde I/O Processor support.// Usage: #include <cyg/hal/hal_verde.h>////####DESCRIPTIONEND####////===========================================================================*/#ifndef CYGONCE_HAL_ARM_XSCALE_HAL_VERDE_H#define CYGONCE_HAL_ARM_XSCALE_HAL_VERDE_H#include <pkgconf/system.h>#include <cyg/hal/hal_xscale.h>// --------------------------------------------------------------------------// Address Translation Unit (Chapter 3)#define ATU_ATUVID REG16(0,0xffffe100)#define ATU_ATUDID REG16(0,0xffffe102)#define ATU_ATUCMD REG16(0,0xffffe104)#define ATU_ATUSR REG16(0,0xffffe106)#define ATU_ATURID REG8(0,0xffffe108)#define ATU_ATUCCR REG8(0,0xffffe109)#define ATU_ATUCLSR REG8(0,0xffffe10c)#define ATU_ATULT REG8(0,0xffffe10d)#define ATU_ATUHTR REG8(0,0xffffe10e)#define ATU_ATUBIST REG8(0,0xffffe10f)#define ATU_IABAR0 REG32(0,0xffffe110)#define ATU_IAUBAR0 REG32(0,0xffffe114)#define ATU_IABAR1 REG32(0,0xffffe118)#define ATU_IAUBAR1 REG32(0,0xffffe11c)#define ATU_IABAR2 REG32(0,0xffffe120)#define ATU_IAUBAR2 REG32(0,0xffffe124)#define ATU_ASVIR REG16(0,0xffffe12c)#define ATU_ASIR REG16(0,0xffffe12e)#define ATU_ERBAR REG32(0,0xffffe130)#define ATU_ATUILR REG8(0,0xffffe13c)#define ATU_ATUIPR REG8(0,0xffffe13d)#define ATU_ATUMGNT REG8(0,0xffffe13e)#define ATU_ATUMLAT REG8(0,0xffffe13f)#define ATU_IALR0 REG32(0,0xffffe140)#define ATU_IATVR0 REG32(0,0xffffe144)#define ATU_ERLR REG32(0,0xffffe148)#define ATU_ERTVR REG32(0,0xffffe14c)#define ATU_IALR1 REG32(0,0xffffe150)#define ATU_IALR2 REG32(0,0xffffe154)#define ATU_IATVR2 REG32(0,0xffffe158)#define ATU_OIOWTVR REG32(0,0xffffe15c)#define ATU_OMWTVR0 REG32(0,0xffffe160)#define ATU_OUMWTVR0 REG32(0,0xffffe164)#define ATU_OMWTVR1 REG32(0,0xffffe168)#define ATU_OUMWTVR1 REG32(0,0xffffe16c)#define ATU_OUDWTVR REG32(0,0xffffe178)#define ATU_ATUCR REG32(0,0xffffe180)#define ATU_PCSR REG32(0,0xffffe184)#define ATU_ATUISR REG32(0,0xffffe188)#define ATU_ATUIMR REG32(0,0xffffe18c)#define ATU_IABAR3 REG32(0,0xffffe190)#define ATU_IAUBAR3 REG32(0,0xffffe194)#define ATU_IALR3 REG32(0,0xffffe198)#define ATU_IATVR3 REG32(0,0xffffe19c)#define ATU_OCCAR REG32(0,0xffffe1a4)#define ATU_OCCDR REG32(0,0xffffe1ac)#define ATU_PDSCR REG32(0,0xffffe1bc)#define ATU_PMCAPID REG8(0,0xffffe1c0)#define ATU_PMNEXT REG8(0,0xffffe1c1)#define ATU_APMCR REG16(0,0xffffe1c2)#define ATU_APMCSR REG16(0,0xffffe1c4)#define ATU_PCIXCAPID REG8(0,0xffffe1e0)#define ATU_PCIXNEXT REG8(0,0xffffe1e1)#define ATU_PCIXCMD REG16(0,0xffffe1e2)#define ATU_PCIXSR REG32(0,0xffffe1e4)#define PCSR_RESET_I_BUS 0x20#define PCSR_RESET_P_BUS 0x10#define PCSR_CFG_RETRY 0x04// --------------------------------------------------------------------------// Application Accelerator Unit (Chapter 6)#define AAU_ACR REG32(0,0xffffe800)#define AAU_ASR REG32(0,0xffffe804)#define AAU_ADAR REG32(0,0xffffe808)#define AAU_ANDAR REG32(0,0xffffe80c)#define AAU_SAR1 REG32(0,0xffffe810)#define AAU_SAR2 REG32(0,0xffffe814)#define AAU_SAR3 REG32(0,0xffffe818)#define AAU_SAR4 REG32(0,0xffffe81c)#define AAU_DAR REG32(0,0xffffe820)#define AAU_ABCR REG32(0,0xffffe824)#define AAU_ADCR REG32(0,0xffffe828)#define AAU_SAR5 REG32(0,0xffffe82c)#define AAU_SAR6 REG32(0,0xffffe830)#define AAU_SAR7 REG32(0,0xffffe834)#define AAU_SAR8 REG32(0,0xffffe838)#define AAU_EDCR0 REG32(0,0xffffe83c)#define AAU_SAR9 REG32(0,0xffffe840)#define AAU_SAR10 REG32(0,0xffffe844)#define AAU_SAR11 REG32(0,0xffffe848)#define AAU_SAR12 REG32(0,0xffffe84c)#define AAU_SAR13 REG32(0,0xffffe850)#define AAU_SAR14 REG32(0,0xffffe854)#define AAU_SAR15 REG32(0,0xffffe858)#define AAU_SAR16 REG32(0,0xffffe85c)#define AAU_EDCR1 REG32(0,0xffffe860)#define AAU_SAR17 REG32(0,0xffffe864)#define AAU_SAR18 REG32(0,0xffffe868)#define AAU_SAR19 REG32(0,0xffffe86c)#define AAU_SAR20 REG32(0,0xffffe870)#define AAU_SAR21 REG32(0,0xffffe874)#define AAU_SAR22 REG32(0,0xffffe878)#define AAU_SAR23 REG32(0,0xffffe87c)#define AAU_SAR24 REG32(0,0xffffe880)#define AAU_EDCR2 REG32(0,0xffffe884)#define AAU_SAR25 REG32(0,0xffffe888)#define AAU_SAR26 REG32(0,0xffffe88c)#define AAU_SAR27 REG32(0,0xffffe890)#define AAU_SAR28 REG32(0,0xffffe894)#define AAU_SAR29 REG32(0,0xffffe898)#define AAU_SAR30 REG32(0,0xffffe89c)#define AAU_SAR31 REG32(0,0xffffe8a0)#define AAU_SAR32 REG32(0,0xffffe8a4)#define AAU_RES0 REG32(0,0xffffe8a8)#define AAU_RES1 REG32(0,0xffffe900)#define AAU_RES2 REG32(0,0xfffff000)#define ACR_ENABLE 1#define ACR_RESUME 2#define ASR_ACTIVE 0x400// --------------------------------------------------------------------------// Memory Controller (Chapter 7)#define MCU_SDIR REG32(0,0xffffe500)#define MCU_SDCR REG32(0,0xffffe504)#define MCU_SDBR REG32(0,0xffffe508)#define MCU_SBR0 REG32(0,0xffffe50c)#define MCU_SBR1 REG32(0,0xffffe510)#define MCU_ECCR REG32(0,0xffffe534)#define MCU_ELOG0 REG32(0,0xffffe538)#define MCU_ELOG1 REG32(0,0xffffe53c)#define MCU_ECAR0 REG32(0,0xffffe540)#define MCU_ECAR1 REG32(0,0xffffe544)#define MCU_ECTST REG32(0,0xffffe548)#define MCU_MCISR REG32(0,0xffffe54c)#define MCU_RFR REG32(0,0xffffe550)#define MCU_DBUDSR REG32(0,0xffffe554)#define MCU_DBDDSR REG32(0,0xffffe558)#define MCU_CUDSR REG32(0,0xffffe55c)#define MCU_CDDSR REG32(0,0xffffe560)#define MCU_CEUDSR REG32(0,0xffffe564)#define MCU_CEDDSR REG32(0,0xffffe568)#define MCU_CSUDSR REG32(0,0xffffe56c)#define MCU_CSDDSR REG32(0,0xffffe570)#define MCU_REUDSR REG32(0,0xffffe574)#define MCU_REDDSR REG32(0,0xffffe578)#define MCU_ABUDSR REG32(0,0xffffe57c)#define MCU_ABDDSR REG32(0,0xffffe580)#define MCU_DSDR REG32(0,0xffffe584)#define MCU_REDR REG32(0,0xffffe588)#define MCU_RES10 REG32(0,0xffffe58c)// Banksize specific component of SBRx register bits#define SBR_32MEG 1#define SBR_64MEG 2#define SBR_128MEG 4#define SBR_256MEG 8#define SBR_512MEG 16// Refresh rates for 200MHz#define RFR_3_9us 0x300#define RFR_7_8us 0x600#define RFR_15_6us 0xC00#define DSDR_REC_VAL 0x00000231#define REDR_REC_VAL 0x00000000#define SDCR_INIT_VAL 0x00000018 // 64-bit - unbuffered DIMM & turn off compensations (SECRET BITS!!!)// SDRAM MODE COMMANDS#define SDIR_CMD_NOP 0x00000005#define SDIR_CMD_PRECHARGE_ALL 0x00000004⌨️ 快捷键说明
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