hal_platform_setup.h

来自「eCos操作系统源码」· C头文件 代码 · 共 951 行 · 第 1/3 页

        // the following DDR SDRAM mode parameters:
        //   a. CAS Latency (CL) = two or two and one-half
        //   b. Wrap Type (WT) = Sequential
        //   c. Burst Length (BL) = four
        NOPs    8

        mov     r1, #SDIR_CMD_CAS_LAT_2_A   // Set CAS Latency to 2
        str     r1, [r0]

        // After waiting T mrd cycles (4 clocks at 200 MHz), issue a precharge-all
        // command to the DDR SDRAM interface by setting the SDIR to 0100.
        NOPs    8

        mov     r1, #SDIR_CMD_PRECHARGE_ALL
        str     r1, [r0]
	
        // After waiting T rp cycles (4 clocks at 200 MHz), provide two 
        // auto-refresh cycles. An auto-refresh cycle is accomplished by 
        // setting the SDIR to 0111. Software must ensure at least T rfc 
        // cycles (16 clocks at 200 MHz) between each auto-refresh command.
        NOPs    8

        mov     r1, #SDIR_CMD_AUTO_REFRESH      // 1st of two auto-refresh cycle commands
        str     r1, [r0]

        NOPs    8

        str     r1, [r0]                        // 2nd of two auto-refresh cycle commands

        NOPs    8   

	// Issues a mode-register-set command by writing to the SDIR to program the
	// DDR SDRAM parameters without resetting the DLL. Setting the SDIR to 0000 
        // programs the MCU for CAS Latency of two while setting the SDIR to 0001
        // programs the MCU for CAS Latency of two and one-half. The MCU supports 
        // the following DDR SDRAM mode parameters:
        //   a. CAS Latency (CL) = two or two and one-half
        //   b. Wrap Type (WT) = Sequential
        //   c. Burst Length (BL) = four
        mov     r1, #SDIR_CMD_CAS_LAT_2_B       // Set CAS Latency to 2
        str     r1, [r0]

        NOPs    8
	
        mov     r1, #0xF                        // DDR Normal Operation
        str     r1, [r0]
	
        // Re-enable the refresh counter by setting the RFR to the required value.
        //
        ldr     r0, =MCU_RFR
        str     r9, [r0]

        // DSDR   - Data Strobe Delay Register                       (Section 7.6.25)
        ldr     r0, =MCU_DSDR
        ldr     r1, =DSDR_REC_VAL
        str     r1, [r0]

        // REDR   - Receive Enable Delay Register                    (Section 7.6.26)
        ldr     r0, =MCU_REDR
        ldr     r1, =REDR_REC_VAL
        str     r1, [r0]

	// ====================================================================
	HEX_DISPLAY r0, r1, DISPLAY_A, DISPLAY_6
	// ====================================================================
		
        // delay before using SDRAM 
        DELAY_FOR 0x1800000, r0
	
	// Enable the Dcache
	mrc	p15, 0, r0, c1, c0, 0
	orr	r0, r0, #MMU_Control_C
	mcr	p15, 0, r0, c1, c0, 0
	CPWAIT  r0

        // Enable branch target buffer
	mrc	p15, 0, r0, c1, c0, 0
	orr	r0, r0, #MMU_Control_BTB
	mcr	p15, 0, r0, c1, c0, 0
	CPWAIT  r0

        mcr     p15, 0, r0, c7, c10, 4  // drain the write & fill buffers
        CPWAIT  r0

        mcr     p15, 0, r0, c7, c7, 0   // flush Icache, Dcache and BTB
        CPWAIT  r0

        mcr     p15, 0, r0, c8, c7, 0   // flush instuction and data TLBs
        CPWAIT  r0

	mcr	p15, 0, r0, c7, c10, 4	// drain the write & fill buffers
	CPWAIT r0	
	
	// ====================================================================
	HEX_DISPLAY r0, r1, DISPLAY_S, DISPLAY_L
	// ====================================================================
	
        ldr     r0, =MCU_ECTST           // clear test register
        mov     r1, #0
        str     r1, [r0]

        ldr     r0, =MCU_ECCR
        mov     r1, #0x0                 // disable ECC, disable reporting
        str     r1, [r0]

#ifdef CYGSEM_HAL_ARM_IQ80321_BATTERY_TEST
	//  Battery Backup SDRAM Memory Test
        //  Move test pattern into register prior to memory scrub
	ldr	r9, =SDRAM_BATTERY_TEST_ADDR
	ldr	r10, [r9]
#endif

	orrs	r14, r14, r14
	beq	no_ecc1

        ldr     r0, =MCU_ECCR
        mov     r1, #0x8                 // enable ECC, disable reporting
        str     r1, [r0]

  no_ecc1:

#ifdef CYGSEM_HAL_ARM_IQ80321_CLEAR_PCI_RETRY
	// Minimally setup ATU and release "retry" bit.
	ldr     r1, =ATU_IATVR2
	mov     r0, #SDRAM_PHYS_BASE
	str     r0, [r1]
	ldr	r0, =0xffffffff
	sub	r1, r4, #1
	sub	r0, r0, r1
	bic	r0, r0, #0x3f
	ldr	r1, =ATU_IALR2
	str     r0, [r1]
	ldr     r0, =((0xFFFFFFFF - ((64 * 1024 * 1024) - 1)) & 0xFFFFFFC0)
        ldr     r1, =ATU_IALR1
	str     r0, [r1]
	mov	r0, #0xc
        ldr     r1, =ATU_IABAR1
	str     r0, [r1]
        ldr     r1, =ATU_IABAR2
        str     r0, [r1]
	mov	r0, #0
        ldr     r1, =ATU_IAUBAR1
	str     r0, [r1]
        ldr     r1, =ATU_PCSR
	ldr	r0, [r1]
	and	r13, r0, #4     // save retry bit for later
	bic	r0, r0, #4
	str	r0, [r1]
#endif
	
        // scrub init
	mov	r12, r4		// size of memory to scrub
	mov	r8, r4		// save DRAM size
        mov     r0, #0
        mov     r1, #0
        mov     r2, #0
        mov     r3, #0
        mov     r4, #0
        mov     r5, #0
        mov     r6, #0
        mov     r7, #0

        ldr     r11, =SDRAM_UNCACHED_BASE

        // scrub Loop
    0:
        stmia   r11!, {r0-r7}
        subs    r12, r12, #32
        bne     0b

	// ====================================================================
	HEX_DISPLAY r0, r1, DISPLAY_S, DISPLAY_E
	// ====================================================================

	// ====================================================================
	HEX_DISPLAY r0, r1, DISPLAY_A, DISPLAY_7
	// ====================================================================

        // clean, drain, flush the main Dcache
        ldr     r1, =DCACHE_FLUSH_AREA  // use a CACHEABLE area of
                                        // memory that's mapped above SDRAM
        mov     r0, #1024               // number of lines in the Dcache
    0:
        mcr     p15, 0, r1, c7, c2, 5   // allocate a Dcache line
        add     r1, r1, #32             // increment to the next cache line
        subs    r0, r0, #1              // decrement the loop count
        bne     0b

	// ====================================================================
	HEX_DISPLAY r0, r1, DISPLAY_A, DISPLAY_8
	// ====================================================================

	// clean, drain, flush the mini Dcache
        ldr     r2, =DCACHE_FLUSH_AREA + DCACHE_SIZE
        mov     r0, #64                 // number of lines in the Dcache
    0:
        mcr     p15, 0, r2, c7, c2, 5   // allocate a Dcache line
        add     r2, r2, #32          // increment to the next cache line
        subs    r0, r0, #1              // decrement the loop count
        bne     0b

        mcr     p15, 0, r0, c7, c6, 0   // flush Dcache
        CPWAIT  r0

        mcr     p15, 0, r0, c7, c10, 4  // drain the write & fill buffers
        CPWAIT  r0

	// ====================================================================
	HEX_DISPLAY r0, r1, DISPLAY_A, DISPLAY_9
	// ====================================================================
	orrs	r14, r14, r14
	beq	no_ecc2
	
        ldr     r0, =MCU_MCISR
        mov     r1, #7
        str     r1, [r0]

        ldr     r0, =MCU_ECCR
        ldr     r1, =0x0f                        // enable ECC
        str     r1, [r0]
	
  no_ecc2:
	
	// ====================================================================
	HEX_DISPLAY r0, r1, DISPLAY_A, DISPLAY_A
	// ====================================================================

#ifdef CYGSEM_HAL_ARM_IQ80321_BATTERY_TEST
	// Battery Backup SDRAM Memory Test
	// Store test pattern back into memory
	str	r10, [r9]
#endif

	// Save SDRAM size
        ldr     r1, =hal_dram_size  /* [see hal_intr.h] */
	str	r8, [r1]

#ifdef CYGSEM_HAL_ARM_IQ80321_CLEAR_PCI_RETRY
	// Save boot time retry flag.
        ldr     r1, =hal_pcsr_cfg_retry
	str	r13, [r1]
#endif

	// Move mmu tables into RAM so page table walks by the cpu
	// don't interfere with FLASH programming.
	ldr	r0, =mmu_table
	add     r2, r0, #0x4000     	// End of tables
	mov	r1, #SDRAM_BASE
	orr	r1, r1, #0x4000		// RAM tables

	// everything can go as-is
    1:
	ldr	r3, [r0], #4
	str	r3, [r1], #4
	cmp	r0, r2
	bne	1b

	// ====================================================================
	HEX_DISPLAY r0, r1, DISPLAY_A, DISPLAY_B
	// ====================================================================

        // clean, drain, flush the main Dcache
        ldr     r1, =DCACHE_FLUSH_AREA  // use a CACHEABLE area of memory
        mov     r0, #1024               // number of lines in the Dcache
    0:
        mcr     p15, 0, r1, c7, c2, 5   // allocate a Dcache line
        add     r1, r1, #32             // increment to the next cache line
        subs    r0, r0, #1              // decrement the loop count
        bne     0b

	// clean, drain, flush the mini Dcache
        ldr     r2, =DCACHE_FLUSH_AREA + DCACHE_SIZE
        mov     r0, #64                 // number of lines in the Dcache
    0:
        mcr     p15, 0, r2, c7, c2, 5   // allocate a Dcache line
        add     r2, r2, #32             // increment to the next cache line
        subs    r0, r0, #1              // decrement the loop count
        bne     0b

        mcr     p15, 0, r0, c7, c6, 0   // flush Dcache
        CPWAIT  r0

        mcr     p15, 0, r0, c7, c10, 4  // drain the write & fill buffers
        CPWAIT  r0

	// ====================================================================
	HEX_DISPLAY r0, r1, DISPLAY_A, DISPLAY_C
	// ====================================================================

	// Set the TTB register to DRAM mmu_table
	ldr	r0, =(SDRAM_PHYS_BASE | 0x4000) // RAM tables
	mov	r1, #0
	mcr	p15, 0, r1, c7, c5, 0		// flush I cache
	mcr	p15, 0, r1, c7, c10, 4		// drain WB
	mcr	p15, 0, r0, c2, c0, 0		// load page table pointer
	mcr	p15, 0, r1, c8, c7, 0		// flush TLBs
	CPWAIT  r0

	// ====================================================================
	HEX_DISPLAY r0, r1, DISPLAY_A, DISPLAY_D
	// ====================================================================
	.endm    // _platform_setup1

#else // defined(CYG_HAL_STARTUP_ROM)
#define PLATFORM_SETUP1
#endif

#define PLATFORM_VECTORS         _platform_vectors
        .macro  _platform_vectors
        .globl  hal_pcsr_cfg_retry
hal_pcsr_cfg_retry:   .long   0  // Boot-time value of PCSR Retry bit.
        .endm                                        

/*---------------------------------------------------------------------------*/
/* end of hal_platform_setup.h                                               */
#endif /* CYGONCE_HAL_PLATFORM_SETUP_H */