vectors.s
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// #========================================================================// #// # vectors.S// #// # Fujitsu exception vectors// #// #========================================================================//####ECOSGPLCOPYRIGHTBEGIN####// -------------------------------------------// This file is part of eCos, the Embedded Configurable Operating System.// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.//// eCos is free software; you can redistribute it and/or modify it under// the terms of the GNU General Public License as published by the Free// Software Foundation; either version 2 or (at your option) any later version.//// eCos is distributed in the hope that it will be useful, but WITHOUT ANY// WARRANTY; without even the implied warranty of MERCHANTABILITY or// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License// for more details.//// You should have received a copy of the GNU General Public License along// with eCos; if not, write to the Free Software Foundation, Inc.,// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.//// As a special exception, if other files instantiate templates or use macros// or inline functions from this file, or you compile this file and link it// with other works to produce a work based on this file, this file does not// by itself cause the resulting work to be covered by the GNU General Public// License. However the source code for this file must still be made available// in accordance with section (3) of the GNU General Public License.//// This exception does not invalidate any other reasons why a work based on// this file might be covered by the GNU General Public License.//// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.// at http://sources.redhat.com/ecos/ecos-license/// -------------------------------------------//####ECOSGPLCOPYRIGHTEND####// #========================================================================// ######DESCRIPTIONBEGIN####// #// # Author(s): gthomas// # Contributors: gthomas// # Date: 2001-09-16// # Purpose: Fujitsu exception vectors// # Description: This file defines the code placed into the exception// # vectors. It also contains the first level default VSRs// # that save and restore state for both exceptions and// # interrupts.// #// #####DESCRIPTIONEND####// #// #========================================================================#include <pkgconf/hal.h>#include CYGBLD_HAL_PLF_DEFS_H #include "frv.inc"#include <cyg/hal/platform.inc> .macro lda a r sethi #gprelhi(\a),\r setlo #gprello(\a),\r add \r,gr16,\r .endm .macro li v r sethi #((\v)>>16),\r setlo #((\v)&0xFFFF),\r .endm .macro save_GDB_exception_regs base,orig // 'orig' points to an area where some registers were already saved // orig+0: GPR4 // orig+4: GPR5 // orig+8: GPR6 // orig+12: GPR16 // orig+16: LR // orig+20: CCR sti gr4,@(\base,_TS_VECTOR) addi \orig,24,gr5 sti gr5,@(\base,_TS_SP) ldi @(\orig,0),gr5 sti gr5,@(\base,_TS_GPR4) ldi @(\orig,4),gr5 sti gr5,@(\base,_TS_GPR5) ldi @(\orig,8),gr5 sti gr5,@(\base,_TS_GPR6) ldi @(\orig,12),gr5 sti gr5,@(\base,_TS_GPR16) ldi @(\orig,16),gr5 sti gr5,@(\base,_TS_LR) ldi @(\orig,20),gr5 sti gr5,@(\base,_TS_CCR) .endm .macro save_exception_regs base sti gr4,@(\base,_TS_VECTOR) sti gr5,@(\base,_TS_GPR5) addi sp,_TS_size,gr5 sti gr5,@(\base,_TS_SP) sti gr6,@(\base,_TS_GPR6) sti gr16,@(\base,_TS_GPR16) movsg lr,gr5 sti gr5,@(\base,_TS_LR) movsg ccr,gr5 sti gr5,@(\base,_TS_CCR) .endm // Save the machine state after an interrupt/exception // Note: it might be possible to use stdi/lddi instructions here, // but it would require that the stack pointer always be 64 bit // (doubleword) aligned. .macro save_state base sti gr0,@(\base,_TS_GPR0) sti gr2,@(\base,_TS_GPR2) sti gr3,@(\base,_TS_GPR3) sti gr7,@(\base,_TS_GPR7) sti gr8,@(\base,_TS_GPR8) sti gr9,@(\base,_TS_GPR9) sti gr10,@(\base,_TS_GPR10) sti gr11,@(\base,_TS_GPR11) sti gr12,@(\base,_TS_GPR12) sti gr13,@(\base,_TS_GPR13) sti gr14,@(\base,_TS_GPR14) sti gr15,@(\base,_TS_GPR15) sti gr17,@(\base,_TS_GPR17) sti gr18,@(\base,_TS_GPR18) sti gr19,@(\base,_TS_GPR19) sti gr20,@(\base,_TS_GPR20) sti gr21,@(\base,_TS_GPR21) sti gr22,@(\base,_TS_GPR22) sti gr23,@(\base,_TS_GPR23) sti gr24,@(\base,_TS_GPR24) sti gr25,@(\base,_TS_GPR25) sti gr26,@(\base,_TS_GPR26) sti gr27,@(\base,_TS_GPR27) sti gr28,@(\base,_TS_GPR28) sti gr29,@(\base,_TS_GPR29) sti gr30,@(\base,_TS_GPR30) sti gr31,@(\base,_TS_GPR31) #if _NGPR != 32 sti gr32,@(\base,_TS_GPR32) sti gr33,@(\base,_TS_GPR33) sti gr34,@(\base,_TS_GPR34) sti gr35,@(\base,_TS_GPR35) sti gr36,@(\base,_TS_GPR36) sti gr37,@(\base,_TS_GPR37) sti gr38,@(\base,_TS_GPR38) sti gr39,@(\base,_TS_GPR39) sti gr40,@(\base,_TS_GPR40) sti gr41,@(\base,_TS_GPR41) sti gr42,@(\base,_TS_GPR42) sti gr43,@(\base,_TS_GPR43) sti gr44,@(\base,_TS_GPR44) sti gr45,@(\base,_TS_GPR45) sti gr46,@(\base,_TS_GPR46) sti gr47,@(\base,_TS_GPR47) sti gr48,@(\base,_TS_GPR48) sti gr49,@(\base,_TS_GPR49) sti gr50,@(\base,_TS_GPR50) sti gr51,@(\base,_TS_GPR51) sti gr52,@(\base,_TS_GPR52) sti gr53,@(\base,_TS_GPR53) sti gr54,@(\base,_TS_GPR54) sti gr55,@(\base,_TS_GPR55) sti gr56,@(\base,_TS_GPR56) sti gr57,@(\base,_TS_GPR57) sti gr58,@(\base,_TS_GPR58) sti gr59,@(\base,_TS_GPR59) sti gr60,@(\base,_TS_GPR60) sti gr61,@(\base,_TS_GPR61) sti gr62,@(\base,_TS_GPR62) sti gr63,@(\base,_TS_GPR63)#endif movsg psr,gr5 sti gr5,@(\base,_TS_PSR) movsg lcr,gr5 sti gr5,@(\base,_TS_LCR) movsg cccr,gr5 sti gr5,@(\base,_TS_CCCR) movsg bpcsr,gr5#if defined( CYGSEM_HAL_FRV_HW_DEBUG ) || defined(CYGPKG_HAL_FRV_FRV400) cmpi gr4,#CYGNUM_HAL_VECTOR_BREAKPOINT,icc0 beq icc0,0,10f#endif 5: movsg pcsr,gr5 cmpi gr4,#CYGNUM_HAL_VECTOR_SYSCALL,icc0 blt icc0,0,10f6: subi gr5,#4,gr5 // traps show PC+410: sti gr5,@(\base,_TS_PC) .endm // Restore the machine state after an interrupt/exception .macro restore_state base,pcreg,retv ldi @(\base,_TS_PC),gr5 movgs gr5,\pcreg ldi @(\base,_TS_CCR),gr5 movgs gr5,ccr ldi @(\base,_TS_LR),gr5 movgs gr5,lr ldi @(\base,_TS_PSR),gr5 movgs gr5,psr ldi @(\base,_TS_LCR),gr5 movgs gr5,lcr ldi @(\base,_TS_CCCR),gr5 movgs gr5,cccr ldi @(\base,_TS_GPR2),gr2 ldi @(\base,_TS_GPR3),gr3 ldi @(\base,_TS_GPR4),gr4 ldi @(\base,_TS_GPR5),gr5 ldi @(\base,_TS_GPR6),gr6 ldi @(\base,_TS_GPR7),gr7 ldi @(\base,_TS_GPR8),gr8 ldi @(\base,_TS_GPR9),gr9 ldi @(\base,_TS_GPR10),gr10 ldi @(\base,_TS_GPR11),gr11 ldi @(\base,_TS_GPR12),gr12 ldi @(\base,_TS_GPR13),gr13 ldi @(\base,_TS_GPR14),gr14 ldi @(\base,_TS_GPR15),gr15 ldi @(\base,_TS_GPR16),gr16 ldi @(\base,_TS_GPR17),gr17 ldi @(\base,_TS_GPR18),gr18 ldi @(\base,_TS_GPR19),gr19 ldi @(\base,_TS_GPR20),gr20 ldi @(\base,_TS_GPR21),gr21 ldi @(\base,_TS_GPR22),gr22 ldi @(\base,_TS_GPR23),gr23 ldi @(\base,_TS_GPR24),gr24 ldi @(\base,_TS_GPR25),gr25 ldi @(\base,_TS_GPR26),gr26 ldi @(\base,_TS_GPR27),gr27 ldi @(\base,_TS_GPR28),gr28 ldi @(\base,_TS_GPR29),gr29 ldi @(\base,_TS_GPR30),gr30 ldi @(\base,_TS_GPR31),gr31#if _NGPR != 32 ldi @(\base,_TS_GPR32),gr32 ldi @(\base,_TS_GPR33),gr33 ldi @(\base,_TS_GPR34),gr34 ldi @(\base,_TS_GPR35),gr35 ldi @(\base,_TS_GPR36),gr36 ldi @(\base,_TS_GPR37),gr37 ldi @(\base,_TS_GPR38),gr38 ldi @(\base,_TS_GPR39),gr39 ldi @(\base,_TS_GPR40),gr40 ldi @(\base,_TS_GPR41),gr41 ldi @(\base,_TS_GPR42),gr42 ldi @(\base,_TS_GPR43),gr43 ldi @(\base,_TS_GPR44),gr44 ldi @(\base,_TS_GPR45),gr45 ldi @(\base,_TS_GPR46),gr46 ldi @(\base,_TS_GPR47),gr47 ldi @(\base,_TS_GPR48),gr48 ldi @(\base,_TS_GPR49),gr49 ldi @(\base,_TS_GPR50),gr50 ldi @(\base,_TS_GPR51),gr51 ldi @(\base,_TS_GPR52),gr52 ldi @(\base,_TS_GPR53),gr53 ldi @(\base,_TS_GPR54),gr54 ldi @(\base,_TS_GPR55),gr55 ldi @(\base,_TS_GPR56),gr56 ldi @(\base,_TS_GPR57),gr57 ldi @(\base,_TS_GPR58),gr58 ldi @(\base,_TS_GPR59),gr59 ldi @(\base,_TS_GPR60),gr60 ldi @(\base,_TS_GPR61),gr61 ldi @(\base,_TS_GPR62),gr62 ldi @(\base,_TS_GPR63),gr63#endif ldi @(\base,_TS_SP),gr1 // This has to be last - Stack pointer rett #\retv .endm #if defined(CYG_HAL_STARTUP_ROM) || defined(CYG_HAL_STARTUP_ROMRAM) .macro exception_VSR#ifdef CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS subi sp,24,sp sti gr4,@(sp,0)#else subi sp,_TS_size,sp sti gr4,@(sp,_TS_GPR4)#endif addi gr0,#((.-8)-_vectors)/16,gr4 bra _exception .endm#if defined(CYGPKG_HAL_FRV_FRV400) && defined(CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS) .macro break_VSR#ifdef CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS subi sp,24,sp sti gr4,@(sp,0)#else subi sp,_TS_size,sp sti gr4,@(sp,_TS_GPR4)#endif addi gr0,#((.-8)-_vectors)/16,gr4 bra _break .endm#endif // CYGPKG_HAL_FRV_FRV400 && STUBS .macro interrupt_VSR subi sp,_TS_size,sp sti gr4,@(sp,_TS_GPR4) addi gr0,#((.-8)-_vectors)/16,gr4 bra _interrupt .endm .section ".rom_vectors","ax"_vectors: call reset_vector nop // I hate fencepost stuff like this.... nop // (NEXT_INDEX_AFTER_THIS - 1) - (PREVIOUS_INDEX_FILLED) nop // (LAST_INDEX_TO_FILL) - (PREVIOUS_INDEX_FILLED) .rept (CYGNUM_HAL_VECTOR_EXTERNAL_INTERRUPT_LEVEL_1-1)-0 exception_VSR .endr .rept (CYGNUM_HAL_VECTOR_EXTERNAL_INTERRUPT_LEVEL_15) - (CYGNUM_HAL_VECTOR_EXTERNAL_INTERRUPT_LEVEL_1-1) interrupt_VSR .endr .rept (254) - CYGNUM_HAL_VECTOR_EXTERNAL_INTERRUPT_LEVEL_15 exception_VSR .endr#if defined(CYGPKG_HAL_FRV_FRV400) && defined(CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS) break_VSR // in index 255#else exception_VSR // another one#endif // CYGPKG_HAL_FRV_FRV400 && STUBS //// Handle a break//// just like _exception, but it calls break_handler instead.//#if defined(CYGPKG_HAL_FRV_FRV400) && defined(CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS) _break: // Save current register state#ifdef CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS sti gr5,@(sp,4) // First, check BRR to see whether we're processing a break // instruction. The stub uses this instruction to enter debug mode. movsg brr,gr5 andicc gr5,#2,gr0,icc0 beq icc0,#0,1f // It is a break instruction. Clear BRR to acknowledge it. movgs gr0,brr // Set LR to the address of the instruction after the break. // Since software breaks are post-execution ones, BPCSR already // contains the right address. movsg bpcsr,gr5 movgs gr5,lr // Restore the other registers and return as if the break were a // call. Don't worry, the user of the break instruction knows // that LR will be clobbered! ldi @(sp,0),gr4 ldi @(sp,4),gr5 addi sp,#24,sp ret1: // We didn't come here from a break instruction so assume a // breakpoint or watchpoint has been triggered. Since the // interrupt and exception handlers save their registers on the // application stack, there's a chance that these handlers could // trigger watchpoints accidentally. We should just ignore // the watchpoint when that happens. // Use the previous value of SPR:ET to decide whether the break // was triggered by stub or user code. The stub runs with traps // disabled, while any user code that disables traps will not be // debuggable. movsg bpsr,gr5 andicc gr5,#1,gr0,icc0 bne icc0,#2,1f // Hmm, it looks like the GDB stub has triggered an old watchpoint. // Acknowledge it by clearing brr and return as if nothing had // happened. movgs gr0,brr ldi @(sp,0),gr4 ldi @(sp,4),gr5 addi sp,#24,sp rett #11: sti gr6,@(sp,8) sti gr16,@(sp,12) movsg lr,gr5 sti gr5,@(sp,16) movsg ccr,gr5 sti gr5,@(sp,20) // Set the global offset register (gr16) call .Lbrk.Lbrk: movsg lr,gr16 sethi #gprelhi(.Lbrk),gr5 setlo #gprello(.Lbrk),gr5 sub gr16,gr5,gr16 mov sp,gr6 // Original stack pointer lda __GDB_stack,gr5 // already on GDB stack? cmp sp,gr5,icc0 bhi icc0,0,10f // no - need to switch lda __GDB_stack_base,gr5 cmp sp,gr5,icc0 bhi icc0,0,11f10: lda __GDB_stack,sp // already on GDB stack?11: subi sp,_TS_size,sp // Space for scratch saves save_GDB_exception_regs sp,gr6 save_state sp#else save_exception_regs sp save_state sp#endif LED 0x0FFF add sp,gr0,gr8 call break_handler restore_state sp,bpcsr,1#endif // CYGPKG_HAL_FRV_FRV400 && STUBS//// Handle an exception//⌨️ 快捷键说明
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