plf_io.h

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} while(0)

#define HAL_PCI_CFG_READ_UINT32( __bus, __devfn, __offset, __val )				\
do {												\
	if ((__bus)==0 && (__devfn)==0) {							\
		HAL_READ_UINT32(0xBE040000+(__offset),(__val));					\
	}											\
	else {											\
		HAL_WRITE_UINT32(0xBFFFFFF8,HAL_PCI_CONFIG_ADDRESS(__bus, __devfn, __offset));	\
		HAL_READ_UINT32(0xBFFFFFFC,(__val));						\
	}											\
} while(0)

// Write a value to the PCI configuration space of the appropriate
// size at an address composed from the bus, devfn and offset.
#define HAL_PCI_CFG_WRITE_UINT8( __bus, __devfn, __offset, __val )				\
do {												\
	if ((__bus)==0 && (__devfn)==0) {							\
		HAL_WRITE_UINT8(0xBE040000+(__offset),(__val));					\
	}											\
	else {											\
		HAL_WRITE_UINT32(0xBFFFFFF8,HAL_PCI_CONFIG_ADDRESS(__bus, __devfn, __offset));	\
		HAL_WRITE_UINT8(0xBFFFFFFC + ((__offset)&3),(__val));				\
	}											\
} while(0)

#define HAL_PCI_CFG_WRITE_UINT16( __bus, __devfn, __offset, __val )				\
do {												\
	if ((__bus)==0 && (__devfn)==0) {							\
		HAL_WRITE_UINT16(0xBE040000+(__offset),(__val));				\
	}											\
	else {											\
		HAL_WRITE_UINT32(0xBFFFFFF8,HAL_PCI_CONFIG_ADDRESS(__bus, __devfn, __offset));	\
		HAL_WRITE_UINT16(0xBFFFFFFC + ((__offset)&2),(__val));				\
	}											\
} while(0)

#define HAL_PCI_CFG_WRITE_UINT32( __bus, __devfn, __offset, __val )				\
do {												\
	if ((__bus)==0 && (__devfn)==0) {							\
		HAL_WRITE_UINT32(0xBE040000+(__offset),(__val));				\
	}											\
	else {											\
		HAL_WRITE_UINT32(0xBFFFFFF8,HAL_PCI_CONFIG_ADDRESS(__bus, __devfn, __offset));	\
		HAL_WRITE_UINT32(0xBFFFFFFC,(__val));						\
	}											\
} while(0)

// Initialize the PCI bus.
#define HAL_PCI_INIT()										  \
do {												  \
	cyg_uint32 devfn;									  \
	cyg_uint16 word;									  \
												  \
	/* we need to set up the bridge _now_ or we won't be able to access the */		  \
	/* PCI config registers */								  \
	HAL_PCI_CFG_READ_UINT32(0,0,CYG_PCI_CFG_COMMAND,word);					  \
	word |= CYG_PCI_CFG_COMMAND_SERR | CYG_PCI_CFG_COMMAND_PARITY;				  \
	word |= CYG_PCI_CFG_COMMAND_MEMORY | CYG_PCI_CFG_COMMAND_IO | CYG_PCI_CFG_COMMAND_MASTER; \
	HAL_PCI_CFG_WRITE_UINT32(0,0,CYG_PCI_CFG_COMMAND,word);					  \
												  \
	HAL_PCI_CFG_WRITE_UINT16(0,0,CYG_PCI_CFG_STATUS,	0xF800);			  \
	HAL_PCI_CFG_WRITE_UINT8 (0,0,CYG_PCI_CFG_LATENCY_TIMER,	0x10);				  \
	HAL_PCI_CFG_WRITE_UINT32(0,0,CYG_PCI_CFG_BAR_0,		0x80000000);			  \
	HAL_PCI_CFG_WRITE_UINT8 (0,0,CYG_PCI_CFG_INT_LINE,	1);				  \
	HAL_PCI_CFG_WRITE_UINT32(0,0,0x48,			0x98000000);			  \
	HAL_PCI_CFG_WRITE_UINT8 (0,0,0x41,			0x00);				  \
	HAL_PCI_CFG_WRITE_UINT8 (0,0,0x42,			0x01);				  \
	HAL_PCI_CFG_WRITE_UINT8 (0,0,0x44,			0x01);				  \
	HAL_PCI_CFG_WRITE_UINT32(0,0,0x50,			0x00000001);			  \
	HAL_PCI_CFG_WRITE_UINT32(0,0,0x58,			0x00000002);			  \
	HAL_PCI_CFG_WRITE_UINT32(0,0,0x5C,			0x00000001);			  \
												  \
	/* we also need to set up the PCI-PCI bridge (no BIOS, you see) */			  \
	devfn = 3<<3 | 0;									  \
												  \
	/* IO: 0x00010000-0x0001ffff */								  \
	HAL_PCI_CFG_WRITE_UINT8 (0,devfn,CYG_PCI_CFG_IO_BASE,		0x01);			  \
	HAL_PCI_CFG_WRITE_UINT16(0,devfn,CYG_PCI_CFG_IO_BASE_UPPER16,	0x0001);		  \
	HAL_PCI_CFG_WRITE_UINT8 (0,devfn,CYG_PCI_CFG_IO_LIMIT,		0xF1);			  \
	HAL_PCI_CFG_WRITE_UINT16(0,devfn,CYG_PCI_CFG_IO_LIMIT_UPPER16,	0x0001);		  \
												  \
	HAL_PCI_CFG_READ_UINT32(0,0,CYG_PCI_CFG_COMMAND,word);					  \
	word |= CYG_PCI_CFG_COMMAND_SERR | CYG_PCI_CFG_COMMAND_PARITY;				  \
	word |= CYG_PCI_CFG_COMMAND_MEMORY | CYG_PCI_CFG_COMMAND_IO | CYG_PCI_CFG_COMMAND_MASTER; \
	HAL_PCI_CFG_WRITE_UINT32(0,0,CYG_PCI_CFG_COMMAND,word);					  \
	HAL_PCI_CFG_WRITE_UINT16(0,devfn,CYG_PCI_CFG_MEM_BASE,		0x1000);		  \
	HAL_PCI_CFG_WRITE_UINT16(0,devfn,CYG_PCI_CFG_MEM_LIMIT,		0x1000);		  \
} while(0)


//-----------------------------------------------------------------------------
// Resources

// Map PCI device resources starting from these addresses in PCI space.
#define HAL_PCI_ALLOC_BASE_MEMORY 0x10000000
#define HAL_PCI_ALLOC_BASE_IO     0x1000

// This is where the PCI spaces are mapped in the CPU's address space.
#define HAL_PCI_PHYSICAL_MEMORY_BASE    0x80000000
#define HAL_PCI_PHYSICAL_IO_BASE        0xBE000000

// Translate the PCI interrupt requested by the device (INTA#, INTB#,
// INTC# or INTD#) to the associated CPU interrupt (i.e., HAL vector).
#define HAL_PCI_TRANSLATE_INTERRUPT( __bus, __devfn, __vec, __valid)          \
    CYG_MACRO_START                                                           \
    cyg_uint8 __req;                                                          \
    HAL_PCI_CFG_READ_UINT8(__bus, __devfn, CYG_PCI_CFG_INT_PIN, __req);       \
    if (0 != __req) {                                                         \
        /* Interrupt assignment as 21285 sees them. (From                 */  \
        /* EBSA285 Eval Board Reference Manual, 3.4 Interrupt Assignment) */  \
        CYG_ADDRWORD __translation[4] = {                                     \
            CYGNUM_HAL_INTERRUPT_RESERVED_170,  /* INTC# */                   \
            CYGNUM_HAL_INTERRUPT_RESERVED_169,  /* INTB# */                   \
            CYGNUM_HAL_INTERRUPT_EXTERNAL_1,    /* INTA# */                   \
            CYGNUM_HAL_INTERRUPT_RESERVED_171}; /* INTD# */                   \
                                                                              \
        /* The PCI lines from the different slots are wired like this  */     \
        /* on the PCI backplane:                                       */     \
        /*                pin6A     pin7B    pin7A   pin8B             */     \
        /* System Slot    INTA#     INTB#    INTC#   INTD#             */     \
        /* I/O Slot 1     INTB#     INTC#    INTD#   INTA#             */     \
        /* I/O Slot 2     INTC#     INTD#    INTA#   INTB#             */     \
        /* I/O Slot 3     INTD#     INTA#    INTB#   INTC#             */     \
        /* I/O Slot 4     INTA#     INTB#    INTC#   INTD#             */     \
        /*                                                             */     \
        /* (From PCI Development Backplane, 3.2.2 Interrupts)          */     \
        /*                                                             */     \
        /* Devsel signals are wired to, resulting in device IDs:       */     \
        /* I/O Slot 1     AD19 / dev 8       [(8+1)&3 = 1]             */     \
        /* I/O Slot 2     AD18 / dev 7       [(7+1)&3 = 0]             */     \
        /* I/O Slot 3     AD17 / dev 6       [(6+1)&3 = 3]             */     \
        /* I/O Slot 4     AD16 / dev 5       [(5+1)&3 = 2]             */     \
        /*                                                             */     \
        /* (From PCI Development Backplane, 3.2.1 General)             */     \
        /*                                                             */     \
        /* The observant reader will notice that the array does not    */     \
        /* match the table of how interrupts are wired. The array      */     \
        /* does however match observed behavior of the hardware:       */     \
        /*                                                             */     \
        /* Observed interrupts with an Intel ethernet card             */     \
        /* put in the slots in turn and set to generate interrupts:    */     \
        /*  slot 1/intA# (dev 8): caused host INTB#                    */     \
        /*  slot 2/intA# (dev 7): caused host INTC#                    */     \
        /*  slot 3/intA# (dev 6): caused host INTD#                    */     \
        /*  slot 4/intA# (dev 5): caused host INTA#                    */     \
                                                                              \
        __vec = __translation[((__req+CYG_PCI_DEV_GET_DEV(__devfn))&3)];      \
        __valid = true;                                                       \
    } else {                                                                  \
        /* Device will not generate interrupt requests. */                    \
        __valid = false;                                                      \
    }                                                                         \
    CYG_MACRO_END


//-----------------------------------------------------------------------------
// Bus address translation macros
#define HAL_PCI_CPU_TO_BUS(__cpu_addr, __bus_addr)            \
    CYG_MACRO_START                                           \
    (__bus_addr) = (CYG_ADDRESS)((cyg_uint32)(__cpu_addr)&~0x20000000);   \
    CYG_MACRO_END

#define HAL_PCI_BUS_TO_CPU(__bus_addr, __cpu_addr)        \
    CYG_MACRO_START                                       \
    (__cpu_addr) = CYGARC_UNCACHED_ADDRESS(__bus_addr);   \
    CYG_MACRO_END

//-----------------------------------------------------------------------------
// end of plf_io.h
#endif // CYGONCE_PLF_IO_H