var_arch.h
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#ifndef CYGONCE_HAL_VAR_ARCH_H#define CYGONCE_HAL_VAR_ARCH_H//==========================================================================//// var_arch.h//// Architecture specific abstractions////==========================================================================//####ECOSGPLCOPYRIGHTBEGIN####// -------------------------------------------// This file is part of eCos, the Embedded Configurable Operating System.// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.//// eCos is free software; you can redistribute it and/or modify it under// the terms of the GNU General Public License as published by the Free// Software Foundation; either version 2 or (at your option) any later version.//// eCos is distributed in the hope that it will be useful, but WITHOUT ANY// WARRANTY; without even the implied warranty of MERCHANTABILITY or// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License// for more details.//// You should have received a copy of the GNU General Public License along// with eCos; if not, write to the Free Software Foundation, Inc.,// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.//// As a special exception, if other files instantiate templates or use macros// or inline functions from this file, or you compile this file and link it// with other works to produce a work based on this file, this file does not// by itself cause the resulting work to be covered by the GNU General Public// License. However the source code for this file must still be made available// in accordance with section (3) of the GNU General Public License.//// This exception does not invalidate any other reasons why a work based on// this file might be covered by the GNU General Public License.//// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.// at http://sources.redhat.com/ecos/ecos-license/// -------------------------------------------//####ECOSGPLCOPYRIGHTEND####//==========================================================================//#####DESCRIPTIONBEGIN####//// Author(s): hmt, nickg// Contributors: nickg// Date: 2001-05-24// Purpose: Define architecture abstractions// Description: This file contains any extra or modified definitions for// this variant of the architecture.// Usage: #include <cyg/hal/var_arch.h>// //####DESCRIPTIONEND####////==========================================================================// -------------------------------------------------------------------------// Although the VR4100 is really a 64 bit CPU, we have defined// target_register_t elsewhere to be 32-bits because we only support// 32-bit mode. Registers will still be sent to GDB as 64-bit, but that's// not relevant for CYG_HAL_GDB_REG.#define CYG_HAL_GDB_REG CYG_WORD32//--------------------------------------------------------------------------// Now defines for all the system controller registers// // These all exist at base 0x1000_0000 in physical memory.#define MIPS_KSEG0_BASE (0x80000000u)#define MIPS_KSEG1_BASE (0xA0000000u)#define UPD985XX_SYSTEM_BASE (0x10000000u)#define MIPS_IO_BASE (MIPS_KSEG1_BASE + UPD985XX_SYSTEM_BASE)#define UPD985XX_SYSCTL_OFF (0x0000u)#define UPD985XX_SYSUSB_OFF (0x1000u)#define UPD985XX_SYSETH_OFF (0x2000u)#define UPD985XX_SYSCTL_REG( n ) ((volatile unsigned int *)\ (MIPS_IO_BASE + UPD985XX_SYSCTL_OFF + (unsigned)(n)))#define UPD985XX_SYSUSB_REG( n ) ((volatile unsigned int *)\ (MIPS_IO_BASE + UPD985XX_SYSUSB_OFF + (unsigned)(n)))#define UPD985XX_SYSETH_REG( n ) ((volatile unsigned int *)\ (MIPS_IO_BASE + UPD985XX_SYSETH_OFF + (unsigned)(n)))// This for the few that we need in assembly#define UPD985XX_SYSCTL_ADDR( n ) (0xb0000000 + (n))// (the noise at the end of these lines is the default value)#define S_GMR UPD985XX_SYSCTL_REG( 0x00) // General Mode Register 00000000H#define S_GSR UPD985XX_SYSCTL_REG( 0x04) // General Status Register unknown#define S_ISR UPD985XX_SYSCTL_REG( 0x08) // Interrupt Status Register 00000000H#define S_IMR UPD985XX_SYSCTL_REG( 0x0C) // Interrupt Mask Register 00000000H#define S_NSR UPD985XX_SYSCTL_REG( 0x10) // NMI Status Register 00000000H#define S_NMR UPD985XX_SYSCTL_REG( 0x14) // NMI Mask Register 00000000H#define S_VER UPD985XX_SYSCTL_REG( 0x18) // Version Register 00000301H// N/A UPD985XX_SYSCTL_REG( 0x1C) reserved 00000000H#define S_GIOER UPD985XX_SYSCTL_REG( 0x20) // GPIO Output Enable Register 00000000H#define S_GOPR UPD985XX_SYSCTL_REG( 0x24) // GPIO Output (Write) Register 00000000H#define S_GIPR UPD985XX_SYSCTL_REG( 0x28) // GPIO Input (Read) Register 00000000H// N/A UPD985XX_SYSCTL_REG( 0x2C) // Reserved unknown#define S_WRCR UPD985XX_SYSCTL_REG( 0x30) // Warm Reset Control Register 00000000H#define S_WRSR UPD985XX_SYSCTL_REG( 0x34) // Warm Reset Status Register 00000000H#define S_PWCR UPD985XX_SYSCTL_REG( 0x38) // Power Control Register 00000000H#define S_PWSR UPD985XX_SYSCTL_REG( 0x3C) // Power Control Status Register 00000000H// N/A UPD985XX_SYSCTL_REG( 0x40) Reserved unknown#define ITCNTR UPD985XX_SYSCTL_REG( 0x4C) // IBUS Timeout Timer Control Register 00000000H#define ITSETR UPD985XX_SYSCTL_REG( 0x50) // IBUS Timeout Timer Set Register 80000000H// N/A UPD985XX_SYSCTL_REG( 0x54) Reserved unknown// UPD985XX_SYSCTL_REG( 0x7F) #define UARTRBR UPD985XX_SYSCTL_REG( 0x80) // UART, Receiver Buffer Register [DLAB=0,READ] unknown#define UARTTHR UPD985XX_SYSCTL_REG( 0x80) // UART, Transmitter Holding Register [DLAB=0,WRITE] unknown#define UARTDLL UPD985XX_SYSCTL_REG( 0x80) // UART, Divisor Latch LSB Register [DLAB=1] unknown#define UARTIER UPD985XX_SYSCTL_REG( 0x84) // UART, Interrupt Enable Register [DLAB=0] unknown#define UARTDLM UPD985XX_SYSCTL_REG( 0x84) // UART, Divisor Latch MSB Register [DLAB=1] unknown#define UARTIIR UPD985XX_SYSCTL_REG( 0x88) // UART, Interrupt ID Register [READ] unknown// The uPD985xx devices do not support UART FIFOs.#define UARTFCR UPD985XX_SYSCTL_REG( 0x88) // UART, FIFO control Register [WRITE]#define UARTLCR UPD985XX_SYSCTL_REG( 0x8C) // UART, Line control Register unknown#define UARTMCR UPD985XX_SYSCTL_REG( 0x90) // UART, Modem Control Register unknown#define UARTLSR UPD985XX_SYSCTL_REG( 0x94) // UART, Line status Register unknown#define UARTMSR UPD985XX_SYSCTL_REG( 0x98) // UART, Modem Status Register unknown#define UARTSCR UPD985XX_SYSCTL_REG( 0x9C) // UART, Scratch Register unknown#define DSUCNTR UPD985XX_SYSCTL_REG( 0xA0) // DSU Control Register 00000000H#define DSUSETR UPD985XX_SYSCTL_REG( 0xA4) // DSU Dead Time Set Register 80000000H#define DSUCLRR UPD985XX_SYSCTL_REG( 0xA8) // DSU Clear Register 00000000H#define DSUTIMR UPD985XX_SYSCTL_REG( 0xAC) // DSU Elapsed Time Register 00000000H#define TMMR UPD985XX_SYSCTL_REG( 0xB0) // Timer Mode Register 00000000H#define TM0CSR UPD985XX_SYSCTL_REG( 0xB4) // Timer CH0 Count Set Register 00000000H#define TM1CSR UPD985XX_SYSCTL_REG( 0xB8) // Timer CH1 Count Set Register 00000000H#define TM0CCR UPD985XX_SYSCTL_REG( 0xBC) // Timer CH0 Current Count Register FFFFFFFFH#define TM1CCR UPD985XX_SYSCTL_REG( 0xC0) // Timer CH1 Current Count Register FFFFFFFFH// N/A UPD985XX_SYSCTL_REG( 0xC4) Reserved unknown// UPD985XX_SYSCTL_REG( 0xCF) #define ECCR UPD985XX_SYSCTL_REG( 0xD0) // EEPROM Command Control Register 00000000H#define ERDR UPD985XX_SYSCTL_REG( 0xD4) // EEPROM Read Data Register 80000000H#define MACAR1 UPD985XX_SYSCTL_REG( 0xD8) // MAC Address Register 1 00000000H#define MACAR2 UPD985XX_SYSCTL_REG( 0xDC) // MAC Address Register 2 00000000H#define MACAR3 UPD985XX_SYSCTL_REG( 0xE0) // MAC Address Register 3 00000000H// N/A UPD985XX_SYSCTL_REG( 0xE4) Reserved unknown// UPD985XX_SYSCTL_REG( 0xFF) #define RMMDR UPD985XX_SYSCTL_REG(0x100) // Boot ROM Mode Register 00000000H#define RMATR UPD985XX_SYSCTL_REG(0x104) // Boot ROM Access Timing Register 00000000H#define SDMDR UPD985XX_SYSCTL_REG(0x108) // SDRAM Mode Register 00000330H#define SDTSR UPD985XX_SYSCTL_REG(0x10C) // SDRAM Type Selection Register 00000000H#define SDPTR UPD985XX_SYSCTL_REG(0x110) // SDRAM Precharge Timing Register 00000142H// N/A UPD985XX_SYSCTL_REG(0x114) ---- ---- Reserved unknown// UPD985XX_SYSCTL_REG(0x11B) #define SDRMR UPD985XX_SYSCTL_REG(0x11C) // SDRAM Refresh Mode Register 00000200H#define SDRCR UPD985XX_SYSCTL_REG(0x120) // SDRAM Refresh Timer Count Register 00000200H#define MBCR UPD985XX_SYSCTL_REG(0x124) // Memory Bus Control Register 00000000H#define MESR UPD985XX_SYSCTL_REG(0x128) // Memory Error Status Register 00000000H#define MEAR UPD985XX_SYSCTL_REG(0x12C) // Memory Error Address Register 00000000H// The few that we need from assembly#define S_ISR_ADR UPD985XX_SYSCTL_ADDR( 0x08) // Interrupt Status Register 00000000H#define S_IMR_ADR UPD985XX_SYSCTL_ADDR( 0x0C) // Interrupt Mask Register 00000000H#define RMMDR_ADR UPD985XX_SYSCTL_ADDR(0x100) // Boot ROM Mode Register 00000000H#define RMATR_ADR UPD985XX_SYSCTL_ADDR(0x104) // Boot ROM Access Timing Register 00000000H#define SDMDR_ADR UPD985XX_SYSCTL_ADDR(0x108) // SDRAM Mode Register 00000330H#define SDTSR_ADR UPD985XX_SYSCTL_ADDR(0x10C) // SDRAM Type Selection Register 00000000H#define SDPTR_ADR UPD985XX_SYSCTL_ADDR(0x110) // SDRAM Precharge Timing Register 00000142H#define SDRMR_ADR UPD985XX_SYSCTL_ADDR(0x11C) // SDRAM Refresh Mode Register 00000200H#define SDRCR_ADR UPD985XX_SYSCTL_ADDR(0x120) // SDRAM Refresh Timer Count Register 00000200H#define MBCR_ADR UPD985XX_SYSCTL_ADDR(0x124) // Memory Bus Control Register 00000000H#define MESR_ADR UPD985XX_SYSCTL_ADDR(0x128) // Memory Error Status Register 00000000H#define MEAR_ADR UPD985XX_SYSCTL_ADDR(0x12C) // Memory Error Address Register 00000000H// ---------------------------------------------------------------------------// Contents of all these glorious registers:// --------- general ---------// S_GMR General Mode Register 00000000H#define S_GMR_CRST 1 // Cold Reset#define S_GMR_IAEN 2 // IBUS Arbiter Enable#define S_GMR_MPFD 4 // Memory-to-CPU Prefetch FIFO disable#define S_GMR_UCSEL 8 // UART Source Clock Selection (0 = CPU, 1 = ext)#define S_GMR_HSWP (1<<8) // HIF Block Data swap function disable#define S_GMR_MSWP (1<<9) // MIF Block Data swap function disable // S_GSR General Status Register#define S_GSR_ENDCEN 1#define S_GSR_CCLKSEL 2⌨️ 快捷键说明
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