plf_io.h
来自「eCos操作系统源码」· C头文件 代码 · 共 357 行 · 第 1/2 页
H
357 行
#define HAL_PCI_CFG_WRITE_UINT8( __bus, __devfn, __offset, __val ) \ cyg_hal_plf_pci_cfg_write_byte((__bus), (__devfn), (__offset), (__val))#define HAL_PCI_CFG_WRITE_UINT16( __bus, __devfn, __offset, __val ) \ cyg_hal_plf_pci_cfg_write_word((__bus), (__devfn), (__offset), (__val))#define HAL_PCI_CFG_WRITE_UINT32( __bus, __devfn, __offset, __val ) \ cyg_hal_plf_pci_cfg_write_dword((__bus), (__devfn), (__offset), (__val))//-----------------------------------------------------------------------------// Resources// Translate the PCI interrupt requested by the device (INTA#, INTB#,// INTC# or INTD#) to the associated CPU interrupt (i.e., HAL vector).// We don't actually know what the mappings are at present for this// board. The following is therefore just a temporary guess until// we can find out.#define HAL_PCI_TRANSLATE_INTERRUPT( __bus, __devfn, __vec, __valid) \ CYG_MACRO_START \ cyg_uint8 __req; \ HAL_PCI_CFG_READ_UINT8(__bus, __devfn, CYG_PCI_CFG_INT_PIN, __req); \ if (0 != __req) { \ CYG_ADDRWORD __translation[4] = { \ CYGNUM_HAL_INTERRUPT_PCI_INTA, /* INTA# */ \ CYGNUM_HAL_INTERRUPT_PCI_INTB, /* INTB# */ \ CYGNUM_HAL_INTERRUPT_PCI_INTC, /* INTC# */ \ CYGNUM_HAL_INTERRUPT_PCI_INTD };/* INTD# */ \ \ __vec = __translation[(((__req-1)+CYG_PCI_DEV_GET_DEV(__devfn))&3)]; \ \ __valid = true; \ } else { \ /* Device will not generate interrupt requests. */ \ __valid = false; \ } \ CYG_MACRO_END// Galileo GT64120 on MIPS Ocelot requires special processing.// First, it will hang when accessing device 31 on the local bus.// Second, we need to ignore the GT64120 so we can set it up// outside the generic PCI library.#define HAL_PCI_IGNORE_DEVICE(__bus, __dev, __fn) \ ((__bus) == 0 && ((__dev) == 0 || (__dev) == 31))//-----------------------------------------------------------------------------// PCI / Galileo register definitions#define HAL_GALILEO_PCI0_CONFIG_ADDR_ConfigEn BIT31#define HAL_GALILEO_PCI0_STATUS_COMMAND_REGNUM 0x04#define HAL_GALILEO_PCI0_BIST_REGNUM 0x0C#define HAL_GALILEO_PCI0_SCS32_BASE_REGNUM 0x14#define HAL_GALILEO_PCI0_CONFIG_MEMEn 0x2#define HAL_GALILEO_PCI0_CONFIG_MasEn 0x4#define HAL_GALILEO_PCI0_CONFIG_SErrEn 0x100#define HAL_GALILEO_PCI0_LAT_TIMER_VAL 0x800#define HAL_GALILEO_PCI0_TIMEOUT_RETRY_VALUE 0x00ffffff#define HAL_GALILEO_PCI_INTERNAL_COMMAND_OFFSET 0xC00#define HAL_GALILEO_PCI0_TIMEOUT_RETRY_OFFSET 0xc04#define HAL_GALILEO_PCI0_SCS10_SIZE_OFFSET 0xc08#define HAL_GALILEO_PCI0_SCS32_SIZE_OFFSET 0xc0c#define HAL_GALILEO_PCI0_SCS20_SIZE_OFFSET 0xc10#define HAL_GALILEO_PCI0_CS3_SIZE_OFFSET 0xc14#define HAL_GALILEO_BAR_ENA_OFFSET 0xc3c# define HAL_GALILEO_BAR_ENA_SWCS3 (1 << 0)# define HAL_GALILEO_BAR_ENA_SWCS32 (1 << 1)# define HAL_GALILEO_BAR_ENA_SWCS10 (1 << 2)# define HAL_GALILEO_BAR_ENA_IO (1 << 3)# define HAL_GALILEO_BAR_ENA_MEM (1 << 4)# define HAL_GALILEO_BAR_ENA_CS3 (1 << 5)# define HAL_GALILEO_BAR_ENA_CS20 (1 << 6)# define HAL_GALILEO_BAR_ENA_SCS32 (1 << 7)# define HAL_GALILEO_BAR_ENA_SCS10 (1 << 8)#define HAL_GALILEO_PCI0_CONFIG_ADDR_OFFSET 0xcf8# define HAL_GALILEO_PCI0_CONFIG_ADDR_ENABLE (1 << 31)#define HAL_GALILEO_PCI0_CONFIG_DATA_OFFSET 0xcfc#define HAL_OCELOT_NULL_DEVNUM 0x0// GALILEO Interrupts#define HAL_GALILEO_IRQ_CAUSE_OFFSET 0xc18# define HAL_GALILEO_IRQCAUSE_INTSUM (1 << 0)# define HAL_GALILEO_IRQCAUSE_MEMOUT (1 << 1)# define HAL_GALILEO_IRQCAUSE_DMAOUT (1 << 2)# define HAL_GALILEO_IRQCAUSE_CPUOUT (1 << 3)# define HAL_GALILEO_IRQCAUSE_DMA0 (1 << 4)# define HAL_GALILEO_IRQCAUSE_DMA1 (1 << 5)# define HAL_GALILEO_IRQCAUSE_DMA2 (1 << 6)# define HAL_GALILEO_IRQCAUSE_DMA3 (1 << 7)# define HAL_GALILEO_IRQCAUSE_T0 (1 << 8)# define HAL_GALILEO_IRQCAUSE_T1 (1 << 9)# define HAL_GALILEO_IRQCAUSE_T2 (1 << 10)# define HAL_GALILEO_IRQCAUSE_T3 (1 << 11)# define HAL_GALILEO_IRQCAUSE_MASRD (1 << 12)# define HAL_GALILEO_IRQCAUSE_SLVWR (1 << 13)# define HAL_GALILEO_IRQCAUSE_MASWR (1 << 14)# define HAL_GALILEO_IRQCAUSE_SLVRD (1 << 15)# define HAL_GALILEO_IRQCAUSE_AERR (1 << 16)# define HAL_GALILEO_IRQCAUSE_MERR (1 << 17)# define HAL_GALILEO_IRQCAUSE_MASABT (1 << 18)# define HAL_GALILEO_IRQCAUSE_TARABT (1 << 19)# define HAL_GALILEO_IRQCAUSE_RETRY (1 << 20)# define HAL_GALILEO_IRQCAUSE_CPUSUM (1 << 30)# define HAL_GALILEO_IRQCAUSE_PCISUM (1 << 31)#define HAL_GALILEO_HIRQ_CAUSE_OFFSET 0xc98#define HAL_GALILEO_CPUIRQ_MASK_OFFSET 0xc1c#define HAL_GALILEO_CPUHIRQ_MASK_OFFSET 0xc9c/* Galileo Memory Controller registers */#define HAL_GALILEO_SDRAM_DUPLICATE_BANK_ADDR BIT20#define HAL_GALILEO_SDRAM_BANK_INTERLEAVE_DIS BIT14#define HAL_GALILEO_CPU_DECODE_SHIFT 21#define HAL_GALILEO_DEV_DECODE_SHIFT 20#define HAL_GALILEO_SDRAM_SRAS_TO_SCAS_DELAY_3C BIT10#define HAL_GALILEO_SDRAM_WIDTH_64BIT BIT6#define HAL_GALILEO_SDRAM_SRAS_PRECHARGE_3C BIT3#define HAL_GALILEO_SDRAM_BANK0_CASLAT_2 BIT0#define HAL_GALILEO_SDRAM_BANK0_SZ_64M BIT11#define HAL_GALILEO_SDRAM_NUM_BANKS_4 BIT5#define HAL_GALILEO_SDRAM_BANK0_PARITY BIT8#define HAL_GALILEO_SDRAM_CFG_RAM_WIDTH BIT15#define HAL_GALILEO_PCI0_CONFIG_ADDR_ConfigEn BIT31#define HAL_GALILEO_PCI0_STATUS_COMMAND_REGNUM 0x04#define HAL_GALILEO_PCI0_BIST_REGNUM 0x0C#define HAL_GALILEO_PCI0_SCS32_BASE_REGNUM 0x14#define HAL_GALILEO_PCI0_CONFIG_MEMEn 0x2#define HAL_GALILEO_PCI0_CONFIG_MasEn 0x4#define HAL_GALILEO_PCI0_CONFIG_SErrEn 0x100#define HAL_GALILEO_PCI0_LAT_TIMER_VAL 0x800#define HAL_GALILEO_PCI0_TIMEOUT_RETRY_VALUE 0x00ffffff#define HAL_GALILEO_SDRAM_BANK0_OFFSET 0x44c#define HAL_GALILEO_SDRAM_BANK2_OFFSET 0x454#define HAL_GALILEO_SDRAM_CONFIG_OFFSET 0x448#define HAL_GALILEO_SCS10_LD_OFFSET 0x008#define HAL_GALILEO_SCS10_HD_OFFSET 0x010#define HAL_GALILEO_SCS32_LD_OFFSET 0x018#define HAL_GALILEO_SCS32_HD_OFFSET 0x020#define HAL_GALILEO_CS20_LD_OFFSET 0x028#define HAL_GALILEO_CS20_HD_OFFSET 0x030#define HAL_GALILEO_PCIIO_LD_OFFSET 0x048#define HAL_GALILEO_PCIIO_HD_OFFSET 0x050#define HAL_GALILEO_PCIMEM0_LD_OFFSET 0x058#define HAL_GALILEO_PCIMEM0_HD_OFFSET 0x060#define HAL_GALILEO_PCIMEM1_LD_OFFSET 0x080#define HAL_GALILEO_PCIMEM1_HD_OFFSET 0x088#define HAL_GALILEO_PCI1IO_LD_OFFSET 0x090#define HAL_GALILEO_PCI1IO_HD_OFFSET 0x098#define HAL_GALILEO_PCI1MEM0_LD_OFFSET 0x0a0#define HAL_GALILEO_PCI1MEM0_HD_OFFSET 0x0a8#define HAL_GALILEO_PCI1MEM1_LD_OFFSET 0x0b0#define HAL_GALILEO_PCI1MEM1_HD_OFFSET 0x0b8#define HAL_GALILEO_PCIIO_REMAP_OFFSET 0x0f0#define HAL_GALILEO_PCIMEM0_REMAP_OFFSET 0x0f8#define HAL_GALILEO_PCIMEM1_REMAP_OFFSET 0x100#define HAL_GALILEO_SCS0_LD_OFFSET 0x400#define HAL_GALILEO_SCS0_HD_OFFSET 0x404#define HAL_GALILEO_SCS1_LD_OFFSET 0x408#define HAL_GALILEO_SCS1_HD_OFFSET 0x40c#define HAL_GALILEO_SCS2_LD_OFFSET 0x410#define HAL_GALILEO_SCS2_HD_OFFSET 0x414#define HAL_GALILEO_SCS3_LD_OFFSET 0x418#define HAL_GALILEO_SCS3_HD_OFFSET 0x41c#define HAL_GALILEO_CS0_LD_OFFSET 0x420#define HAL_GALILEO_CS0_HD_OFFSET 0x424#define HAL_GALILEO_CS1_LD_OFFSET 0x428#define HAL_GALILEO_CS1_HD_OFFSET 0x42c#define HAL_GALILEO_CS2_LD_OFFSET 0x430#define HAL_GALILEO_CS2_HD_OFFSET 0x434#define HAL_GALILEO_CPU_DECODE_SHIFT 21//-----------------------------------------------------------------------------// end of plf_io.h#endif // CYGONCE_PLF_IO_H⌨️ 快捷键说明
复制代码Ctrl + C
搜索代码Ctrl + F
全屏模式F11
增大字号Ctrl + =
减小字号Ctrl + -
显示快捷键?