plf_io.h

来自「eCos操作系统源码」· C头文件 代码 · 共 357 行 · 第 1/2 页

#ifndef CYGONCE_PLF_IO_H
#define CYGONCE_PLF_IO_H

//=============================================================================
//
//      plf_io.h
//
//      Platform specific IO support
//
//=============================================================================
//####ECOSGPLCOPYRIGHTBEGIN####
// -------------------------------------------
// This file is part of eCos, the Embedded Configurable Operating System.
// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
//
// eCos is free software; you can redistribute it and/or modify it under
// the terms of the GNU General Public License as published by the Free
// Software Foundation; either version 2 or (at your option) any later version.
//
// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or
// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
// for more details.
//
// You should have received a copy of the GNU General Public License along
// with eCos; if not, write to the Free Software Foundation, Inc.,
// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
//
// As a special exception, if other files instantiate templates or use macros
// or inline functions from this file, or you compile this file and link it
// with other works to produce a work based on this file, this file does not
// by itself cause the resulting work to be covered by the GNU General Public
// License. However the source code for this file must still be made available
// in accordance with section (3) of the GNU General Public License.
//
// This exception does not invalidate any other reasons why a work based on
// this file might be covered by the GNU General Public License.
//
// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
// at http://sources.redhat.com/ecos/ecos-license/
// -------------------------------------------
//####ECOSGPLCOPYRIGHTEND####
//=============================================================================
//#####DESCRIPTIONBEGIN####
//
// Author(s):    hmt, jskov, nickg
// Contributors: hmt, jskov, nickg
// Date:         1999-08-09
// Purpose:      Ocelot/Galileo GT-64120A PCI IO support macros
// Description: 
// Usage:        #include <cyg/hal/plf_io.h>
//
// Note:         Based on information in 
//               "Galileo GT 64120A System Controller For 
//                RC4650/4700/5000 and RM526X/527X/7000 CPUs"
//####DESCRIPTIONEND####
//
//=============================================================================

#include <pkgconf/hal.h>

#include <cyg/hal/hal_arch.h>           // address macros
#include <cyg/hal/hal_io.h>             // IO macros
#include <cyg/hal/hal_intr.h>           // Interrupt vectors

//-----------------------------------------------------------------------------
// PCI access registers

//#define HAL_PCI_ADDRESS_WINDOW_1        0xAF000014
//#define HAL_PCI_ADDRESS_WINDOW_2        0xAF000018
//#define HAL_PCI_IO_WINDOW               0xAF000024
#define HAL_PCI_CONFIG_SPACE_DATA       0xb4000cfc
#define HAL_PCI_CONFIG_SPACE_ADDR       0xb4000cf8
//#define HAL_PCI_ENABLE_REG              0xAF000074

//-----------------------------------------------------------------------------
// Mappings for PCI memory and IO spaces

// These are the offsets programmed into the Galileo for setting up the
// CPU->PCI space mapping. These are put high to allow for 256MB RAM in
// kseg0/1 - but we'll probably have to put the RAM in kuseg anyway to get
// it all mapped (512MB). These mappings leave enough space for the
// PCI devices on the Ocelot regardless though.
//
// Note that the CPU addresses are going directly to the PCI bus, so
// the IO/MEM bases are the matching CPU address space locations, not
// zero.

#define HAL_OCELOT_PCI_IO_BASE                  0x10000000
#define HAL_OCELOT_PCI_IO_SIZE                  0x01000000  // 16 MB
#define HAL_OCELOT_PCI_MEM0_BASE                0x12000000
#define HAL_OCELOT_PCI_MEM0_SIZE                0x01000000  // 16 MB
#define HAL_OCELOT_PCI_MEM1_BASE                0x13000000
#define HAL_OCELOT_PCI_MEM1_SIZE                0x01000000  // 16 MB

// This is where the PCI spaces are mapped in the CPU's (virtual)
// address space. These are the uncached addresses.
#define HAL_PCI_PHYSICAL_MEMORY_BASE            CYGARC_UNCACHED_ADDRESS(0)
#define HAL_PCI_PHYSICAL_IO_BASE                CYGARC_UNCACHED_ADDRESS(0)

// Map PCI device resources starting from these addresses in PCI space.
#define HAL_PCI_ALLOC_BASE_MEMORY               HAL_OCELOT_PCI_MEM0_BASE
#define HAL_PCI_ALLOC_BASE_IO                   HAL_OCELOT_PCI_IO_BASE


// Uncached controller base
#define HAL_GALILEO_CONTROLLER_BASE             0xb4000000

//-----------------------------------------------------------------------------

#define HAL_GALILEO_PUTREG(r,d) \
    HAL_WRITE_UINT32((HAL_GALILEO_CONTROLLER_BASE + (r)), \
                     ((((d) & 0xff) << 24) | (((d) & 0xff00) << 8) | (((d) & 0xff0000) >> 8) | (((d) >> 24) & 0xff)))
#define HAL_GALILEO_GETREG(r)   \
    ({ cyg_uint32 d; HAL_READ_UINT32((HAL_GALILEO_CONTROLLER_BASE + (r)), d);\
       (((d & 0xff) << 24) | ((d & 0xff00) << 8) | ((d & 0xff0000) >> 8) | ((d >> 24) & 0xff)); })

// PCI config reads are special: all devices but the Galileo itself
// are in big-endian mode.  Fiddling the endian configs did not seem
// to make a difference.
#define HAL_GALILEO_PUTPCI(bus, devfn, r, data)                         \
    CYG_MACRO_START                                                     \
    if (0 == bus && 0 == devfn)                                         \
        HAL_GALILEO_PUTREG(r, data);                                    \
    else                                                                \
        HAL_WRITE_UINT32((HAL_GALILEO_CONTROLLER_BASE + (r)), data);    \
    CYG_MACRO_END

#define HAL_GALILEO_GETPCI(bus, devfn, r, data)                         \
    CYG_MACRO_START                                                     \
    if (0 == bus && 0 == devfn)                                         \
        data = HAL_GALILEO_GETREG(r);                                   \
    else                                                                \
        HAL_READ_UINT32((HAL_GALILEO_CONTROLLER_BASE + (r)), data);     \
    CYG_MACRO_END


extern cyg_uint32 cyg_hal_plf_pci_cfg_read_dword (cyg_uint32 bus,
						  cyg_uint32 devfn,
						  cyg_uint32 offset);
extern cyg_uint16 cyg_hal_plf_pci_cfg_read_word  (cyg_uint32 bus,
						  cyg_uint32 devfn,
						  cyg_uint32 offset);
extern cyg_uint8 cyg_hal_plf_pci_cfg_read_byte   (cyg_uint32 bus,
						  cyg_uint32 devfn,
						  cyg_uint32 offset);
extern void cyg_hal_plf_pci_cfg_write_dword (cyg_uint32 bus,
					     cyg_uint32 devfn,
					     cyg_uint32 offset,
					     cyg_uint32 val);
extern void cyg_hal_plf_pci_cfg_write_word  (cyg_uint32 bus,
					     cyg_uint32 devfn,
					     cyg_uint32 offset,
					     cyg_uint16 val);
extern void cyg_hal_plf_pci_cfg_write_byte   (cyg_uint32 bus,
					      cyg_uint32 devfn,
					      cyg_uint32 offset,
					      cyg_uint8 val);

//-----------------------------------------------------------------------------

// Initialize the PCI bus.
externC void cyg_hal_plf_pci_init(void);
#define HAL_PCI_INIT() cyg_hal_plf_pci_init()

// Read a value from the PCI configuration space of the appropriate
// size at an address composed from the bus, devfn and
// offset.
#define HAL_PCI_CFG_READ_UINT8( __bus, __devfn, __offset, __val )  \
    __val = cyg_hal_plf_pci_cfg_read_byte((__bus),  (__devfn), (__offset))
    
#define HAL_PCI_CFG_READ_UINT16( __bus, __devfn, __offset, __val ) \
    __val = cyg_hal_plf_pci_cfg_read_word((__bus),  (__devfn), (__offset))

#define HAL_PCI_CFG_READ_UINT32( __bus, __devfn, __offset, __val ) \
    __val = cyg_hal_plf_pci_cfg_read_dword((__bus),  (__devfn), (__offset))

// Write a value to the PCI configuration space of the appropriate
// size at an address composed from the bus, devfn and offset.