hal_cache.h

来自「eCos操作系统源码」· C头文件 代码 · 共 431 行 · 第 1/2 页

    { _HAL_ASM_DCACHE_ALL_WAYS(0x01, _addr_); }                         \
    _HAL_ASM_SET_MIPS_ISA(0);                                           \
    CYG_MACRO_END
#endif

// Set the data cache refill burst size
//#define HAL_DCACHE_BURST_SIZE(_size_)

// Set the data cache write mode
//#define HAL_DCACHE_WRITE_MODE( _mode_ )

//#define HAL_DCACHE_WRITETHRU_MODE       0
//#define HAL_DCACHE_WRITEBACK_MODE       1

// Load the contents of the given address range into the data cache
// and then lock the cache so that it stays there.
// This uses the fetch-and-lock cache operation.
#ifndef HAL_DCACHE_LOCK_DEFINED
#define HAL_DCACHE_LOCK(_base_, _asize_)                                    \
    CYG_MACRO_START                                                         \
    register CYG_ADDRESS _addr_  = HAL_DCACHE_START_ADDRESS(_base_);        \
    register CYG_ADDRESS _eaddr_ = HAL_DCACHE_END_ADDRESS(_base_, _asize_); \
    register CYG_WORD _state_;                                              \
    HAL_DCACHE_IS_ENABLED( _state_ );                                       \
    if( _state_ ) {                                                         \
        _HAL_ASM_SET_MIPS_ISA(3);                                           \
        for( ; _addr_ < _eaddr_; _addr_ += HAL_DCACHE_LINE_SIZE )           \
        { _HAL_ASM_DCACHE_ALL_WAYS(0x1d, _addr_); }                         \
        _HAL_ASM_SET_MIPS_ISA(0);                                           \
    }                                                                       \
    CYG_MACRO_END
#endif

// Undo a previous lock operation.
// Do this by flushing the cache, which is defined to clear the lock bit.
#ifndef HAL_DCACHE_UNLOCK_DEFINED
#define HAL_DCACHE_UNLOCK(_base_, _size_) \
        HAL_DCACHE_FLUSH( _base_, _size_ )
#endif

// Unlock entire cache
#ifndef HAL_DCACHE_UNLOCK_ALL_DEFINED
#define HAL_DCACHE_UNLOCK_ALL() \
        HAL_DCACHE_INVALIDATE_ALL()
#endif

//-----------------------------------------------------------------------------
// Data cache line control

// Allocate cache lines for the given address range without reading its
// contents from memory.
//#define HAL_DCACHE_ALLOCATE( _base_ , _size_ )

// Write dirty cache lines to memory and invalidate the cache entries
// for the given address range.
// This uses the hit-writeback-invalidate cache operation.
#ifndef HAL_DCACHE_FLUSH_DEFINED
#define HAL_DCACHE_FLUSH( _base_ , _asize_ )                                \
    CYG_MACRO_START                                                         \
    register CYG_ADDRESS _addr_  = HAL_DCACHE_START_ADDRESS(_base_);        \
    register CYG_ADDRESS _eaddr_ = HAL_DCACHE_END_ADDRESS(_base_, _asize_); \
    register CYG_WORD _state_;                                              \
    HAL_DCACHE_IS_ENABLED( _state_ );                                       \
    if( _state_ ) {                                                         \
        _HAL_ASM_SET_MIPS_ISA(3);                                           \
        for( ; _addr_ < _eaddr_; _addr_ += HAL_DCACHE_LINE_SIZE )           \
        { _HAL_ASM_DCACHE_ALL_WAYS(0x15, _addr_); }                         \
        _HAL_ASM_SET_MIPS_ISA(0);                                           \
    }                                                                       \
    CYG_MACRO_END
#endif

// Invalidate cache lines in the given range without writing to memory.
// This uses the hit-invalidate cache operation.
#ifndef HAL_DCACHE_INVALIDATE_DEFINED
#define HAL_DCACHE_INVALIDATE( _base_ , _asize_ )                           \
    CYG_MACRO_START                                                         \
    register CYG_ADDRESS _addr_  = HAL_DCACHE_START_ADDRESS(_base_);        \
    register CYG_ADDRESS _eaddr_ = HAL_DCACHE_END_ADDRESS(_base_, _asize_); \
    _HAL_ASM_SET_MIPS_ISA(3);                                               \
    for( ; _addr_ < _eaddr_; _addr_ += HAL_DCACHE_LINE_SIZE )               \
    { _HAL_ASM_DCACHE_ALL_WAYS(0x11, _addr_); }                             \
    _HAL_ASM_SET_MIPS_ISA(0);                                               \
    CYG_MACRO_END
#endif

// Write dirty cache lines to memory for the given address range.
// This uses the hit-writeback cache operation.
#ifndef HAL_DCACHE_STORE_DEFINED
#define HAL_DCACHE_STORE( _base_ , _asize_ )                                \
    CYG_MACRO_START                                                         \
    register CYG_ADDRESS _addr_  = HAL_DCACHE_START_ADDRESS(_base_);        \
    register CYG_ADDRESS _eaddr_ = HAL_DCACHE_END_ADDRESS(_base_, _asize_); \
    register CYG_WORD _state_;                                              \
    HAL_DCACHE_IS_ENABLED( _state_ );                                       \
    if( _state_ ) {                                                         \
        _HAL_ASM_SET_MIPS_ISA(3);                                           \
        for( ; _addr_ < _eaddr_; _addr_ += HAL_DCACHE_LINE_SIZE )           \
        { _HAL_ASM_DCACHE_ALL_WAYS(0x19, _addr_); }                         \
        _HAL_ASM_SET_MIPS_ISA(0);                                           \
    }                                                                       \
    CYG_MACRO_END
#endif

// Preread the given range into the cache with the intention of reading
// from it later.
//#define HAL_DCACHE_READ_HINT( _base_ , _size_ )

// Preread the given range into the cache with the intention of writing
// to it later.
//#define HAL_DCACHE_WRITE_HINT( _base_ , _size_ )

// Allocate and zero the cache lines associated with the given range.
//#define HAL_DCACHE_ZERO( _base_ , _size_ )

//-----------------------------------------------------------------------------
// Global control of Instruction cache

// Enable the instruction cache
// There is no default mechanism for enabling or disabling the caches.
#ifndef HAL_ICACHE_ENABLE_DEFINED
#define HAL_ICACHE_ENABLE()
#endif

// Disable the instruction cache
#ifndef HAL_ICACHE_DISABLE_DEFINED
#define HAL_ICACHE_DISABLE()
#endif

#ifndef HAL_ICACHE_IS_ENABLED_DEFINED
#define HAL_ICACHE_IS_ENABLED(_state_) (_state_) = 1;
#endif

// Invalidate the entire cache
// This uses the index-invalidate cache operation.
#ifndef HAL_ICACHE_INVALIDATE_ALL_DEFINED
#define HAL_ICACHE_INVALIDATE_ALL()                                           \
    CYG_MACRO_START                                                           \
    register CYG_ADDRESS _baddr_ = 0x80000000;                                \
    register CYG_ADDRESS _addr_ = 0x80000000;                                 \
    _HAL_ASM_SET_MIPS_ISA(3);                                                 \
    for( ; _addr_ < _baddr_+HAL_ICACHE_SIZE; _addr_ += HAL_ICACHE_LINE_SIZE ) \
    { _HAL_ASM_ICACHE_ALL_WAYS(0x00, _addr_); }                               \
    _HAL_ASM_SET_MIPS_ISA(0);                                                 \
    CYG_MACRO_END
#endif

// Synchronize the contents of the cache with memory.
// Simply force the cache to reload.
#ifndef HAL_ICACHE_SYNC_DEFINED
#define HAL_ICACHE_SYNC() HAL_ICACHE_INVALIDATE_ALL()
#endif

// Set the instruction cache refill burst size
//#define HAL_ICACHE_BURST_SIZE(_size_)

// Load the contents of the given address range into the instruction cache
// and then lock the cache so that it stays there.
// This uses the fetch-and-lock cache operation.
#ifndef HAL_ICACHE_LOCK_DEFINED
#define HAL_ICACHE_LOCK(_base_, _asize_)                                    \
    CYG_MACRO_START                                                         \
    register CYG_ADDRESS _addr_  = HAL_ICACHE_START_ADDRESS(_base_);        \
    register CYG_ADDRESS _eaddr_ = HAL_ICACHE_END_ADDRESS(_base_, _asize_); \
    register CYG_WORD _state_;                                              \
    HAL_ICACHE_IS_ENABLED( _state_ );                                       \
    if( _state_ ) {                                                         \
        _HAL_ASM_SET_MIPS_ISA(3);                                           \
        for( ; _addr_ < _eaddr_; _addr_ += HAL_ICACHE_LINE_SIZE )           \
        { _HAL_ASM_ICACHE_ALL_WAYS(0x1c, _addr_); }                         \
        _HAL_ASM_SET_MIPS_ISA(0);                                           \
    }                                                                       \
    CYG_MACRO_END
#endif

// Undo a previous lock operation.
// Do this by invalidating the cache, which is defined to clear the lock bit.
#ifndef HAL_ICACHE_UNLOCK_DEFINED
#define HAL_ICACHE_UNLOCK(_base_, _size_) \
        HAL_ICACHE_INVALIDATE( _base_, _size_ )
#endif

// Unlock entire cache
//#define HAL_ICACHE_UNLOCK_ALL()

//-----------------------------------------------------------------------------
// Instruction cache line control

// Invalidate cache lines in the given range without writing to memory.
// This uses the hit-invalidate cache operation.
#ifndef HAL_ICACHE_INVALIDATE_DEFINED
#define HAL_ICACHE_INVALIDATE( _base_ , _asize_ )                           \
    CYG_MACRO_START                                                         \
    register CYG_ADDRESS _addr_  = HAL_ICACHE_START_ADDRESS(_base_);        \
    register CYG_ADDRESS _eaddr_ = HAL_ICACHE_END_ADDRESS(_base_, _asize_); \
    _HAL_ASM_SET_MIPS_ISA(3);                                               \
    for( ; _addr_ < _eaddr_; _addr_ += HAL_ICACHE_LINE_SIZE )               \
    { _HAL_ASM_ICACHE_ALL_WAYS(0x10, _addr_); }                             \
    _HAL_ASM_SET_MIPS_ISA(0);                                               \
    CYG_MACRO_END
#endif

//-----------------------------------------------------------------------------
// Check that a supported configuration has actually defined some macros.

#ifndef HAL_DCACHE_ENABLE

#error Unsupported MIPS configuration

#endif

//-----------------------------------------------------------------------------
#endif // ifndef CYGONCE_HAL_CACHE_H
// End of hal_cache.h