sh4_202_md.sgml

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      </varlistentry>
    </variablelist>

  </refsect1>

  <refsect1 id="sh4-microdev-config-redboot"><title>RedBoot and Virtual Vectors</title>
    <para>
If the application is intended to act as a ROM monitor, providing
services for other applications, then the configuration option
<varname>CYGSEM_HAL_ROM_MONITOR</varname> should be set. Typically
this option is set only when building RedBoot.
    </para>
    <para>
If the application is supposed to make use of services provided by a
ROM monitor, via the eCos virtual vector mechanism, then the
configuration option <varname>CYGSEM_HAL_USE_ROM_MONITOR</varname>
should be set. By default this option is enabled when building for a
RAM startup, disabled otherwise. It can be manually disabled for a RAM
startup, making the application self-contained, as a testing step
before switching to ROM startup.
    </para>
    <para>
If the application does not rely on a ROM monitor for diagnostic
services then the serial port will be claimed for HAL
diagnostics.
    </para>
  </refsect1>

  <refsect1 id="sh4-microdev-config-flash"><title>Flash Driver</title>
    <para>
The MicroDev board contains 32Mb of Intel StrataFlash, specifically,
two E28F128 parts in parallel. The
<varname>CYGPKG_DEVS_FLASH_STRATA</varname> package contains all the
code necessary to support these parts and the
<varname>CYGPKG_DEVS_FLASH_SH_MICRODEV</varname> package contains
definitions that customize the driver to the MicroDev board.
    </para>
    <para>
Note that if booting from EEPROM instead of flash, the flash driver will
not be able to detect or use the flash parts.
    </para>
  </refsect1>

  <refsect1 id="sh4-microdev-config-eth"><title>Ethernet Driver</title>
    <para>
The MicroDev board contains an SMSC LAN91C111 ethernet device.
The
<varname>CYGPKG_DEVS_ETH_SMSC_LAN91CXX</varname> package contains all the
code necessary to support this part and the
<varname>CYGPKG_DEVS_ETH_SH_MICRODEV</varname> package contains
definitions that customize the driver to the MicroDev board.
    </para>
  </refsect1>


  <refsect1 id="sh4-microdev-config-clock"><title>System Clock</title>
    <para>
By default, the system clock interrupts once every 10ms, corresponding
to a 100Hz clock. This can be changed by the configuration option
<varname>CYGNUM_HAL_RTC_DENOMINATOR</varname> which corresponds to the
clock frequency. Other clock-related settings are recalculated
automatically if the denominator is changed.
    </para>
  </refsect1>

  <refsect1 id="sh4-microdev-config-flags"><title>Compiler Flags</title>
    <para>
The platform HAL defines the default compiler and linker flags for all
packages, although it is possible to override these on a per-package
basis. Most of the flags used are the same as for other architectures
supported by eCos. There are two flags specific to this port:
    </para>
    <variablelist>
      <varlistentry>
        <term><option>-m4</option></term>
        <listitem><para>
The <application>sh-elf-gcc</application> compiler supports many
variants of the SH architecture, from the SH2 onwards.
A <option>-m</option> option should be used to select the specific
variant in use, and with current tools <option>-m4</option> is the
correct option for the SH4-202.
        </para></listitem>
      </varlistentry>
<!-- DOES THIS APPLY?
      <varlistentry>
        <term><option>-fomit-frame-pointer</option></term>
        <listitem><para>
Traditionally the <varname>R14</varname> register was used as a
dedicated frame pointer, and the compiler was expected to keep it up
to date
on procedure entry and exit. These days
the compiler is perfectly capable of generating working code without a
frame pointer, so omitting the frame pointer often saves some work
during procedure entry and exit and makes another register available
for optimization. However without a frame pointer register the
<application>sh-elf-gdb</application> debugger is not always able to
interpret a thread stack, so it cannot reliably give a backtrace.
Removing <option>-fomit-frame-pointer</option> from the default flags
will make debugging easier, but the generated code may be worse.
        </para></listitem>
      </varlistentry>
-->
    </variablelist>
  </refsect1>
 
</refentry>

<!-- }}} -->
<!-- {{{ Port                           -->

<refentry id="sh4-microdev-port">
  <refmeta>
    <refentrytitle>The HAL Port</refentrytitle>
  </refmeta>
  <refnamediv>
    <refname>HAL Port</refname>
    <refpurpose>Implementation Details</refpurpose>
  </refnamediv>

  <refsect1 id="sh4-microdev-port-overview"><title>Overview</title>
    <para>
This documentation explains how the eCos HAL specification has been
mapped onto the MicroDev hardware, and should be read in conjunction
with that specification. The MicroDev platform HAL package complements
the SH architectural HAL and the SH4 variant HAL. It provides
functionality which is specific to the target board.
    </para>
  </refsect1>

  <refsect1 id="sh4-microdev-port-startup"><title>Startup</title>
    <para>
Following a hard or soft reset the HAL will initialize or
reinitialize most of the on-chip peripherals. There is an exception
for RAM startup applications which depend on a ROM monitor for certain
services.
    </para>
    <para>
For ROM startup, the HAL will perform additional initialization,
setting up the external DRAM and programming the various internal
registers. The values used for most of these registers are assigned
fixed values from a table in the header <filename
class="headerfile">cyg/hal/platform.inc</filename>.
    </para>
  </refsect1>

  <refsect1 id="sh4-microdev-port-linker"><title>Linker Scripts and Memory Maps</title>
    <para>
The platform HAL package provides the memory layout information needed
to generate the linker script. The key memory locations are as follows:
    </para>
    <variablelist>
      <varlistentry>
        <term>off-chip Flash</term>
        <listitem><para>
This is located at address 0x00000000 of the physical memory space and is
therefore accessible in the P1 region at location 0x80000000. An
uncached shadow of this memory is available in the P2 region at 0xA0000000.
The contents of the flash are organized as described earlier.
        </para></listitem>
      </varlistentry>
      <varlistentry>
        <term>off-chip EEPROM</term>
        <listitem>
        <para>
If selected by the DIP switches, this occupies the same addresses as the
off-chip flash, and the flash is no longer visible.
        </para>
        </listitem>
      </varlistentry>
      <varlistentry>
        <term>external SDRAM</term>
        <listitem>
        <para>
This is located at address 0x08000000 of the physical memory space and is
therefore accessable in the P1 region at location 0x88000000. An
uncached shadow of this memory is available in the P2 region at 0xA8000000. The
first 256 bytes are used for hardware exception vectors. The next 256
bytes are normally used for the eCos virtual vectors, allowing
RAM-based applications to use services provided by the ROM
monitor. For ROM startup, all remaining SDRAM is available. For RAM
startup, available SDRAM starts at location 0x80100000, with the bottom
1MB reserved for use by RedBoot.
        </para>
        </listitem>
      </varlistentry>
      <varlistentry>
        <term>on-chip peripherals</term>
        <listitem><para>
These are accessible  via the P4 region at location 0xE0000000 onwards.
        </para></listitem>
      </varlistentry>
      <varlistentry>
        <term>off-chip peripherals</term>
        <listitem><para>
The ethernet device is located at 0xA7500000. The FPGA interrupt
controller is located at 0x06110000. These are the only
off-chip peripherals accessed by eCos. All others are left
untouched.
        </para></listitem>
      </varlistentry>
    </variablelist>
  </refsect1>

  <refsect1 id="sh4-microdev-port-clock"><title>Clock Support</title>
    <para>
The platform HAL provides configuration options for the eCos system
clock. This always uses the hardware timer 0, which should not be used
directly by application code. Timer 1 is used to implement a
microsecond resolution busy delay service. Timer 2 is not used by eCos
so application code is free to manipulate this as required. The
actual HAL macros for managing the clock are provided by the SH architecture
processor HAL.
    </para>
    <para>
There is a software model of the structure of the SH family clock
supply subsystem which performs the correct calculations to yield not
only the inputs for the CPU clock but also the peripheral clocks fed
to the serial device, memory controllers and other devices. The values
for the master crystal, the PLL multipliers and various dividers are
supplied by the platform HAL. Some care must be taken in defining
these since wrong values will cause the timers and the SCIF baud rate
to be miscalculated. If the OSCAR chip switches are changed from the
default then the value of <varname>CYGHWR_HAL_SH_OOC_XTAL</varname>
must be changed to match.
    </para>
  </refsect1>

  <refsect1 id="sh4-microdev-port-other-hal"><title>Other Issues</title>
    <para>
The MicroDev platform HAL does not affect the implementation of other
parts of the eCos HAL specification. The
SH4 variant HAL, and the SH architectural HAL documentation
should be consulted for further details.
    </para>
    <para>
It should be noted that the floating point support in the SH HAL has a
caveat that, if the FPSCR register is changed, it may get reverted at a
later stage by certain operations performed by the GCC compiler. This
behaviour is intentional as the alternative would be to update the GCC
compiler's internal state about the FPSCR at every context switch which
would be expensive for a feature that is unlikely to be used frequently.
If the FPSCR is to be changed by the application, the developer
should call the function <function>__set_fpscr(int)</function>, passing it
the new FPSCR value.
    </para>
  </refsect1>

</refentry>

<!-- }}} -->

</part>