hal_sh_sh7729_hs7729pci.cdl

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# ====================================================================##      hal_sh_sh7729_hs7729pci.cdl##      Hitachi HS7729PCI board HAL package configuration data## ====================================================================#####ECOSGPLCOPYRIGHTBEGIN###### -------------------------------------------## This file is part of eCos, the Embedded Configurable Operating System.## Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.#### eCos is free software; you can redistribute it and/or modify it under## the terms of the GNU General Public License as published by the Free## Software Foundation; either version 2 or (at your option) any later version.#### eCos is distributed in the hope that it will be useful, but WITHOUT ANY## WARRANTY; without even the implied warranty of MERCHANTABILITY or## FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License## for more details.#### You should have received a copy of the GNU General Public License along## with eCos; if not, write to the Free Software Foundation, Inc.,## 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.#### As a special exception, if other files instantiate templates or use macros## or inline functions from this file, or you compile this file and link it## with other works to produce a work based on this file, this file does not## by itself cause the resulting work to be covered by the GNU General Public## License. However the source code for this file must still be made available## in accordance with section (3) of the GNU General Public License.#### This exception does not invalidate any other reasons why a work based on## this file might be covered by the GNU General Public License.#### Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.## at http://sources.redhat.com/ecos/ecos-license/## -------------------------------------------#####ECOSGPLCOPYRIGHTEND##### ====================================================================######DESCRIPTIONBEGIN###### Author(s):      jskov# Original data:  jskov# Contributors:# Date:           2001-05-25######DESCRIPTIONEND###### ====================================================================cdl_package CYGPKG_HAL_SH_SH7729_HS7729PCI {    display       "Hitachi/SH7729 HS7729PCI board"    parent        CYGPKG_HAL_SH    requires      CYGPKG_HAL_SH_7729    requires      ! CYGHWR_HAL_SH_BIGENDIAN    requires      CYGHWR_HAL_SH_IRQ_USE_IRQLVL    requires      { !CYGPKG_REDBOOT || CYGDAT_REDBOOT_SH_LINUX_BOOT_ENTRY == 0x8c211000 }    requires      { !CYGPKG_REDBOOT || CYGDAT_REDBOOT_SH_LINUX_BOOT_BASE_ADDR == 0x8c210000 }    define_header hal_sh_sh7729_hs7729pci.h    include_dir   cyg/hal    description   "        The HS7729PCI HAL package provides the support needed to run        eCos on a Hitachi/SH HS7729PCI board."    compile       hal_diag.c plf_misc.c ser16c550c.c smsc37c93x.c    implements    CYGINT_HAL_DEBUG_GDB_STUBS    implements    CYGINT_HAL_DEBUG_GDB_STUBS_BREAK    implements    CYGINT_HAL_VIRTUAL_VECTOR_SUPPORT    implements    CYGINT_HAL_VIRTUAL_VECTOR_COMM_BAUD_SUPPORT    define_proc {        puts $::cdl_system_header "#define CYGBLD_HAL_TARGET_H   <pkgconf/hal_sh.h>"        puts $::cdl_system_header "#define CYGBLD_HAL_PLATFORM_H <pkgconf/hal_sh_sh7729_hs7729pci.h>"        puts $::cdl_header "#define CYGNUM_HAL_SH_SH3_SCIF_PORTS 1"        puts $::cdl_header "#define CYGHWR_HAL_VSR_TABLE 0x8c000000"        puts $::cdl_header "#define CYGHWR_HAL_VECTOR_TABLE 0x8c000100"	puts $::cdl_header "#define HAL_PLATFORM_CPU    \"SH 7729\""        puts $::cdl_header "#define HAL_PLATFORM_BOARD  \"HS7729PCI\""        puts $::cdl_header "#define HAL_PLATFORM_EXTRA  \"\""    }    cdl_component CYG_HAL_STARTUP {        display       "Startup type"        flavor        data        legal_values  {"RAM" "ROM" "ROMRAM" }        default_value {"RAM"}	no_define	define -file system.h CYG_HAL_STARTUP        description   "           When targetting the HS7729PCI board it is possible to build           the system for either RAM bootstrap or ROM bootstrap.           RAM bootstrap generally requires that the board           is equipped with ROMs containing a suitable ROM monitor or           equivalent software that allows GDB to download the eCos           application on to the board. The ROM bootstrap typically           requires that the eCos application be blown into EPROMs or           equivalent technology. ROMRAM bootstrap is similar to ROM           bootstrap, but everything is copied to RAM before execution            starts thus improving performance, but at the cost of an           increased RAM footprint."    }    cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_COMM_CHANNELS {        display      "Number of communication channels on the board"        flavor       data        calculated   3    }    cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_DEBUG_CHANNEL {        display          "Debug serial port"        flavor data        legal_values     0 to CYGNUM_HAL_VIRTUAL_VECTOR_COMM_CHANNELS-1        default_value    0        description      "           The HS7729PCI board has one serial port. This option           chooses which port will be used to connect to a host           running GDB."    }    cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_DEFAULT {        display      "Default console channel."        flavor       data        calculated   0    }    cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL {        display          "Diagnostic serial port"        flavor data        legal_values     0 to CYGNUM_HAL_VIRTUAL_VECTOR_COMM_CHANNELS-1        default_value    CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_DEFAULT        description      "           The HS7729PCI board has two serial ports.  This option           chooses which port will be used for diagnostic output."    }    cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_CHANNELS_DEFAULT_BAUD {        display       "Console/GDB serial port baud rate"        flavor        data        legal_values  9600 19200 38400 57600 115200        default_value 38400        define           CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_BAUD        description   "            This option controls the default baud rate used for the            Console/GDB connection."    }    cdl_component CYGHWR_HAL_SH_PLF_CLOCK_SETTINGS {        display          "SH on-chip platform clock controls"        description      "            The various clocks used by the system are derived from            these options."        flavor        none        no_define                             cdl_option CYGHWR_HAL_SH_OOC_XTAL {            display          "SH clock crystal"            flavor           data            legal_values     8000000 to 50000000            default_value    33000000            no_define            description      "                This option specifies the frequency of the crystal all                other clocks are derived from."        }        cdl_option CYGHWR_HAL_SH_OOC_PLL_1 {            display          "SH clock PLL circuit 1"            flavor           data            default_value    4            legal_values     { 0 1 2 3 4 6 8 }            description      "                This selects the multiplication factor provided by                PLL1. If PLL1 is disabled via CAP1, this option should                be set to zero."        }        cdl_option CYGHWR_HAL_SH_OOC_PLL_2 {            display          "SH clock PLL circuit 2"            flavor           data            default_value    1            legal_values     { 0 1 4 }            no_define            description      "                This selects the multiplication factor provided by

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