var_misc.c

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        iprX &= ~CYGARC_REG_IPRE_DMAC_MASK;                              
        iprX |= (level)*CYGARC_REG_IPRE_DMAC_PRI1;                     
        HAL_WRITE_UINT16(CYGARC_REG_IPRE, iprX);                         
        break;                                                           
    case CYGNUM_HAL_INTERRUPT_IRDA_ERI1:                                 
    case CYGNUM_HAL_INTERRUPT_IRDA_RXI1:                                 
    case CYGNUM_HAL_INTERRUPT_IRDA_BRI1:                                 
    case CYGNUM_HAL_INTERRUPT_IRDA_TXI1:                                 
        HAL_READ_UINT16(CYGARC_REG_IPRE, iprX);                          
        iprX &= ~CYGARC_REG_IPRE_IRDA_MASK;                              
        iprX |= (level)*CYGARC_REG_IPRE_IRDA_PRI1;                     
        HAL_WRITE_UINT16(CYGARC_REG_IPRE, iprX);                         
        break;                                                           
    case CYGNUM_HAL_INTERRUPT_SCIF_ERI2:                                 
    case CYGNUM_HAL_INTERRUPT_SCIF_RXI2:                                 
    case CYGNUM_HAL_INTERRUPT_SCIF_BRI2:                                 
    case CYGNUM_HAL_INTERRUPT_SCIF_TXI2:                                 
        HAL_READ_UINT16(CYGARC_REG_IPRE, iprX);                          
        iprX &= ~CYGARC_REG_IPRE_SCIF_MASK;                              
        iprX |= (level)*CYGARC_REG_IPRE_SCIF_PRI1;                     
        HAL_WRITE_UINT16(CYGARC_REG_IPRE, iprX);                         
        break;                                                           
    case CYGNUM_HAL_INTERRUPT_ADC_ADI:                                   
        HAL_READ_UINT16(CYGARC_REG_IPRE, iprX);                          
        iprX &= ~CYGARC_REG_IPRE_ADC_MASK;                               
        iprX |= (level)*CYGARC_REG_IPRE_ADC_PRI1;                      
        HAL_WRITE_UINT16(CYGARC_REG_IPRE, iprX);                         
        break;                                                           
#endif // (CYGARC_SH_MOD_INTC >= 2)

#if (CYGARC_SH_MOD_INTC >= 3)
        /* IPRF */                                                           
    case CYGNUM_HAL_INTERRUPT_LCDC_LCDI:                                 
        HAL_READ_UINT16(CYGARC_REG_IPRF, iprX);                          
        iprX &= ~CYGARC_REG_IPRF_LCDI_MASK;                              
        iprX |= (level)*CYGARC_REG_IPRF_LCDI_PRI1;                     
        HAL_WRITE_UINT16(CYGARC_REG_IPRF, iprX);                         
        break;                                                           
    case CYGNUM_HAL_INTERRUPT_PCC_PCC0:                                  
        HAL_READ_UINT16(CYGARC_REG_IPRF, iprX);                          
        iprX &= ~CYGARC_REG_IPRF_PCC0_MASK;                              
        iprX |= (level)*CYGARC_REG_IPRF_PCC0_PRI1;                     
        HAL_WRITE_UINT16(CYGARC_REG_IPRF, iprX);                         
        break;                                                           
    case CYGNUM_HAL_INTERRUPT_PCC_PCC1:                                  
        HAL_READ_UINT16(CYGARC_REG_IPRF, iprX);                          
        iprX &= ~CYGARC_REG_IPRF_PCC1_MASK;                              
        iprX |= (level)*CYGARC_REG_IPRF_PCC1_PRI1;                     
        HAL_WRITE_UINT16(CYGARC_REG_IPRF, iprX);                         
        break;                                                           
#endif // (CYGARC_SH_MOD_INTC >= 3)

    case CYGNUM_HAL_INTERRUPT_RESERVED_1E0:                              
    case CYGNUM_HAL_INTERRUPT_RESERVED_3E0:                              
        /* Do nothing for these reserved vectors. */                     
        break;                                                           

    // Platform extensions
    CYGPRI_HAL_INTERRUPT_UPDATE_LEVEL_PLF(vector, level)

    default:
        CYG_FAIL("Unknown interrupt vector");                             
        break;
    }                                                                    
}

void
hal_interrupt_set_level(int vector, int level)
{
    CYG_ASSERT((0 <= (level) && 15 >= (level)), "Illegal level");    
    CYG_ASSERT((CYGNUM_HAL_ISR_MIN <= (vector)                         
                && CYGNUM_HAL_ISR_MAX >= (vector)), "Illegal vector"); 
                                                                         
    cyg_hal_ILVL_table[vector] = level;

    hal_interrupt_update_level(vector);
}

void
hal_interrupt_mask(int vector)                                    
{
    switch( (vector) ) {                                                
    case CYGNUM_HAL_INTERRUPT_NMI:                                        
        /* fall through */                                                
    case CYGNUM_HAL_INTERRUPT_LVL0 ... CYGNUM_HAL_INTERRUPT_LVL14:
        /* Normally can only be masked by fiddling Imask in SR,
           but some platforms use external interrupt controller,
           so allow regular handling. */
        // fall through
    case CYGNUM_HAL_INTERRUPT_TMU0_TUNI0 ... CYGNUM_HAL_ISR_MAX:            
        cyg_hal_IMASK_table[vector] = 0;
        hal_interrupt_update_level(vector);
        break;                                                            
    case CYGNUM_HAL_INTERRUPT_RESERVED_1E0:                               
    case CYGNUM_HAL_INTERRUPT_RESERVED_3E0:                               
        /* Do nothing for these reserved vectors. */                      
        break;                                                            
    default:                                                              
        CYG_FAIL("Unknown interrupt vector");                             
        break;                                                            
    }                                                                     
}

void
hal_interrupt_unmask(int vector)                                  
{
    switch( (vector) ) {                                                
    case CYGNUM_HAL_INTERRUPT_NMI:                                        
        /* fall through */                                                
    case CYGNUM_HAL_INTERRUPT_LVL0 ... CYGNUM_HAL_INTERRUPT_LVL14:          
        /* Normally can only be masked by fiddling Imask in SR,
           but some platforms use external interrupt controller,
           so allow regular handling. */
        // fall through
    case CYGNUM_HAL_INTERRUPT_TMU0_TUNI0 ... CYGNUM_HAL_ISR_MAX:            
        cyg_hal_IMASK_table[vector] = 1;
        hal_interrupt_update_level(vector);
        break;                                                            
    case CYGNUM_HAL_INTERRUPT_RESERVED_1E0:                               
    case CYGNUM_HAL_INTERRUPT_RESERVED_3E0:                               
        /* Do nothing for these reserved vectors. */                      
        break;                                                            
    default:                                                              
        CYG_FAIL("Unknown interrupt vector");                             
        break;                                                            
    }                                                                     
}

void
hal_interrupt_acknowledge(int vector)
{
#if (CYGARC_SH_MOD_INTC >= 2)
    if ( (vector) >= CYGNUM_HAL_INTERRUPT_IRQ_IRQ0                      
         && (vector) <= CYGNUM_HAL_INTERRUPT_IRQ_IRQ5) {                
                                                                          
        cyg_uint8 irr0;                                                   
                                                                          
        HAL_READ_UINT8(CYGARC_REG_IRR0, irr0);       
        switch ( vector ) {                          
#ifndef CYGHWR_HAL_SH_IRQ_USE_IRQLVL                 
        case CYGNUM_HAL_INTERRUPT_IRQ_IRQ0:          
            irr0 &= ~CYGARC_REG_IRR0_IRQ0;           
            break;                                   
        case CYGNUM_HAL_INTERRUPT_IRQ_IRQ1:          
            irr0 &= ~CYGARC_REG_IRR0_IRQ1;           
            break;                                   
        case CYGNUM_HAL_INTERRUPT_IRQ_IRQ2:          
            irr0 &= ~CYGARC_REG_IRR0_IRQ2;           
            break;                                   
        case CYGNUM_HAL_INTERRUPT_IRQ_IRQ3:          
            irr0 &= ~CYGARC_REG_IRR0_IRQ3;           
            break;                                   
#endif                                               
        case CYGNUM_HAL_INTERRUPT_IRQ_IRQ4:          
            irr0 &= ~CYGARC_REG_IRR0_IRQ4;           
            break;                                   
        case CYGNUM_HAL_INTERRUPT_IRQ_IRQ5:          
            irr0 &= ~CYGARC_REG_IRR0_IRQ5;           
            break;                                   
        default:                                     
            CYG_FAIL("Unhandled interrupt vector");  
        }                                            
        HAL_WRITE_UINT8(CYGARC_REG_IRR0, irr0);      
    }                                                                     
#endif

    CYGPRI_HAL_INTERRUPT_ACKNOWLEDGE_PLF(vector);
}

// Note: The PINTs can be masked and configured individually, even
// though there are only two vectors. Maybe add some fake vectors just
// for masking/configuring?
void 
hal_interrupt_configure(int vector, int level, int up)
{
#if (CYGARC_SH_MOD_INTC >= 2)
    if ( (vector) >= CYGNUM_HAL_INTERRUPT_IRQ_IRQ0                     
         && (vector) <= CYGNUM_HAL_INTERRUPT_IRQ_IRQ5) {               
                                                                         
        cyg_uint16 icr1, ss, mask;                                       
        ss = 0;                                                          
        mask = CYGARC_REG_ICR1_SENSE_UP|CYGARC_REG_ICR1_SENSE_LEVEL;     
        if (up) ss |= CYGARC_REG_ICR1_SENSE_UP;                        
        if (level) ss |= CYGARC_REG_ICR1_SENSE_LEVEL;                  
        CYG_ASSERT(!(up && level), "Cannot trigger on high level!"); 
                                                                         
        switch( (vector) ) {                                           
        case CYGNUM_HAL_INTERRUPT_IRQ_IRQ5:                              
            ss <<= CYGARC_REG_ICR1_SENSE_IRQ5_shift;                     
            mask <<= CYGARC_REG_ICR1_SENSE_IRQ5_shift;                   
            break;                                                       
        case CYGNUM_HAL_INTERRUPT_IRQ_IRQ4:                              
            ss <<= CYGARC_REG_ICR1_SENSE_IRQ4_shift;                     
            mask <<= CYGARC_REG_ICR1_SENSE_IRQ4_shift;                   
            break;                                                       
#ifndef CYGHWR_HAL_SH_IRQ_USE_IRQLVL
        case CYGNUM_HAL_INTERRUPT_IRQ_IRQ3:                              
            ss <<= CYGARC_REG_ICR1_SENSE_IRQ3_shift;                     
            mask <<= CYGARC_REG_ICR1_SENSE_IRQ3_shift;                   
            break;                                                       
        case CYGNUM_HAL_INTERRUPT_IRQ_IRQ2:                              
            ss <<= CYGARC_REG_ICR1_SENSE_IRQ2_shift;                     
            mask <<= CYGARC_REG_ICR1_SENSE_IRQ2_shift;                   
            break;                                                       
        case CYGNUM_HAL_INTERRUPT_IRQ_IRQ1:                              
            ss <<= CYGARC_REG_ICR1_SENSE_IRQ1_shift;                     
            mask <<= CYGARC_REG_ICR1_SENSE_IRQ1_shift;                   
            break;                                                       
        case CYGNUM_HAL_INTERRUPT_IRQ_IRQ0:                              
            ss <<= CYGARC_REG_ICR1_SENSE_IRQ0_shift;                     
            mask <<= CYGARC_REG_ICR1_SENSE_IRQ0_shift;                   
            break;                                                       
#endif
        default:
            CYG_FAIL("Unhandled interrupt vector");
        }
                                                                         
        HAL_READ_UINT16(CYGARC_REG_ICR1, icr1);                          
        icr1 &= ~mask;                                                   
        icr1 |= ss;                                                      
        HAL_WRITE_UINT16(CYGARC_REG_ICR1, icr1);                         
    }                                                                    
#endif

    CYGPRI_HAL_INTERRUPT_CONFIGURE_PLF(vector, level, up);
}

//---------------------------------------------------------------------------
// End of hal_misc.c