var_misc.c

来自「eCos操作系统源码」· C语言 代码 · 共 802 行 · 第 1/2 页

        HAL_WRITE_UINT16(CYGARC_REG_IPRC, iprX);
        break;
    case CYGNUM_HAL_INTERRUPT_DMAC3_DEI3:
        HAL_READ_UINT16(CYGARC_REG_IPRC, iprX);
        iprX &= ~CYGARC_REG_IPRC_DMAC3_MASK;
        iprX |= (level)*CYGARC_REG_IPRC_DMAC3_PRI1;
        HAL_WRITE_UINT16(CYGARC_REG_IPRC, iprX);
        break;

        /* IPRD */
    case CYGNUM_HAL_INTERRUPT_MTU0_TGI0A:
    case CYGNUM_HAL_INTERRUPT_MTU0_TGI0B:
    case CYGNUM_HAL_INTERRUPT_MTU0_TGI0C:
    case CYGNUM_HAL_INTERRUPT_MTU0_TGI0D:
        HAL_READ_UINT16(CYGARC_REG_IPRD, iprX);
        iprX &= ~CYGARC_REG_IPRD_MTU0A_MASK;
        iprX |= (level)*CYGARC_REG_IPRD_MTU0A_PRI1;
        HAL_WRITE_UINT16(CYGARC_REG_IPRD, iprX);
        break;
    case CYGNUM_HAL_INTERRUPT_MTU0_TGI0V:
        HAL_READ_UINT16(CYGARC_REG_IPRD, iprX);
        iprX &= ~CYGARC_REG_IPRD_MTU0B_MASK;
        iprX |= (level)*CYGARC_REG_IPRD_MTU0B_PRI1;
        HAL_WRITE_UINT16(CYGARC_REG_IPRD, iprX);
        break;
    case CYGNUM_HAL_INTERRUPT_MTU1_TGI1A:
    case CYGNUM_HAL_INTERRUPT_MTU1_TGI1B:
        HAL_READ_UINT16(CYGARC_REG_IPRD, iprX);
        iprX &= ~CYGARC_REG_IPRD_MTU1A_MASK;
        iprX |= (level)*CYGARC_REG_IPRD_MTU1A_PRI1;
        HAL_WRITE_UINT16(CYGARC_REG_IPRD, iprX);
        break;
    case CYGNUM_HAL_INTERRUPT_MTU1_TGI1V:
    case CYGNUM_HAL_INTERRUPT_MTU1_TGI1U:
        HAL_READ_UINT16(CYGARC_REG_IPRD, iprX);
        iprX &= ~CYGARC_REG_IPRD_MTU1B_MASK;
        iprX |= (level)*CYGARC_REG_IPRD_MTU1B_PRI1;
        HAL_WRITE_UINT16(CYGARC_REG_IPRD, iprX);
        break;

        /* IPRE */
    case CYGNUM_HAL_INTERRUPT_MTU2_TGI2A:
    case CYGNUM_HAL_INTERRUPT_MTU2_TGI2B:
        HAL_READ_UINT16(CYGARC_REG_IPRE, iprX);
        iprX &= ~CYGARC_REG_IPRE_MTU2A_MASK;
        iprX |= (level)*CYGARC_REG_IPRE_MTU2A_PRI1;
        HAL_WRITE_UINT16(CYGARC_REG_IPRE, iprX);
        break;
    case CYGNUM_HAL_INTERRUPT_MTU2_TGI2V:
    case CYGNUM_HAL_INTERRUPT_MTU2_TGI2U:
        HAL_READ_UINT16(CYGARC_REG_IPRE, iprX);
        iprX &= ~CYGARC_REG_IPRE_MTU2B_MASK;
        iprX |= (level)*CYGARC_REG_IPRE_MTU2B_PRI1;
        HAL_WRITE_UINT16(CYGARC_REG_IPRE, iprX);
        break;
    case CYGNUM_HAL_INTERRUPT_MTU3_TGI3A:
    case CYGNUM_HAL_INTERRUPT_MTU3_TGI3B:
    case CYGNUM_HAL_INTERRUPT_MTU3_TGI3C:
    case CYGNUM_HAL_INTERRUPT_MTU3_TGI3D:
        HAL_READ_UINT16(CYGARC_REG_IPRE, iprX);
        iprX &= ~CYGARC_REG_IPRE_MTU3A_MASK;
        iprX |= (level)*CYGARC_REG_IPRE_MTU3A_PRI1;
        HAL_WRITE_UINT16(CYGARC_REG_IPRE, iprX);
        break;
    case CYGNUM_HAL_INTERRUPT_MTU3_TGI3V:
        HAL_READ_UINT16(CYGARC_REG_IPRE, iprX);
        iprX &= ~CYGARC_REG_IPRE_MTU3B_MASK;
        iprX |= (level)*CYGARC_REG_IPRE_MTU3B_PRI1;
        HAL_WRITE_UINT16(CYGARC_REG_IPRE, iprX);
        break;

        /* IPRF */
    case CYGNUM_HAL_INTERRUPT_MTU4_TGI4A:
    case CYGNUM_HAL_INTERRUPT_MTU4_TGI4B:
    case CYGNUM_HAL_INTERRUPT_MTU4_TGI4C:
    case CYGNUM_HAL_INTERRUPT_MTU4_TGI4D:
        HAL_READ_UINT16(CYGARC_REG_IPRF, iprX);
        iprX &= ~CYGARC_REG_IPRF_MTU4A_MASK;
        iprX |= (level)*CYGARC_REG_IPRF_MTU4A_PRI1;
        HAL_WRITE_UINT16(CYGARC_REG_IPRF, iprX);
        break;
    case CYGNUM_HAL_INTERRUPT_MTU4_TGI4V:
        HAL_READ_UINT16(CYGARC_REG_IPRF, iprX);
        iprX &= ~CYGARC_REG_IPRF_MTU4B_MASK;
        iprX |= (level)*CYGARC_REG_IPRF_MTU4B_PRI1;
        HAL_WRITE_UINT16(CYGARC_REG_IPRF, iprX);
        break;
    case CYGNUM_HAL_INTERRUPT_SCI0_ERI0:
    case CYGNUM_HAL_INTERRUPT_SCI0_RXI0:
    case CYGNUM_HAL_INTERRUPT_SCI0_TXI0:
    case CYGNUM_HAL_INTERRUPT_SCI0_TEI0:
        HAL_READ_UINT16(CYGARC_REG_IPRF, iprX);
        iprX &= ~CYGARC_REG_IPRF_SCI0_MASK;
        iprX |= (level)*CYGARC_REG_IPRF_SCI0_PRI1;
        HAL_WRITE_UINT16(CYGARC_REG_IPRF, iprX);
        break;
    case CYGNUM_HAL_INTERRUPT_SCI1_ERI1:
    case CYGNUM_HAL_INTERRUPT_SCI1_RXI1:
    case CYGNUM_HAL_INTERRUPT_SCI1_TXI1:
    case CYGNUM_HAL_INTERRUPT_SCI1_TEI1:
        HAL_READ_UINT16(CYGARC_REG_IPRF, iprX);
        iprX &= ~CYGARC_REG_IPRF_SCI1_MASK;
        iprX |= (level)*CYGARC_REG_IPRF_SCI1_PRI1;
        HAL_WRITE_UINT16(CYGARC_REG_IPRF, iprX);
        break;

        /* IPRG */
    case CYGNUM_HAL_INTERRUPT_AD_ADI0:
    case CYGNUM_HAL_INTERRUPT_AD_ADI1:
        HAL_READ_UINT16(CYGARC_REG_IPRG, iprX);
        iprX &= ~CYGARC_REG_IPRG_AD_MASK;
        iprX |= (level)*CYGARC_REG_IPRG_AD_PRI1;
        HAL_WRITE_UINT16(CYGARC_REG_IPRG, iprX);
        break;
    case CYGNUM_HAL_INTERRUPT_DTC_SWDTCE:
        HAL_READ_UINT16(CYGARC_REG_IPRG, iprX);
        iprX &= ~CYGARC_REG_IPRG_DTC_MASK;
        iprX |= (level)*CYGARC_REG_IPRG_DTC_PRI1;
        HAL_WRITE_UINT16(CYGARC_REG_IPRG, iprX);
        break;
    case CYGNUM_HAL_INTERRUPT_CMT0_CMI0:
        HAL_READ_UINT16(CYGARC_REG_IPRG, iprX);
        iprX &= ~CYGARC_REG_IPRG_CMT0_MASK;
        iprX |= (level)*CYGARC_REG_IPRG_CMT0_PRI1;
        HAL_WRITE_UINT16(CYGARC_REG_IPRG, iprX);
        break;
    case CYGNUM_HAL_INTERRUPT_CMT1_CMI1:
        HAL_READ_UINT16(CYGARC_REG_IPRG, iprX);
        iprX &= ~CYGARC_REG_IPRG_CMT1_MASK;
        iprX |= (level)*CYGARC_REG_IPRG_CMT1_PRI1;
        HAL_WRITE_UINT16(CYGARC_REG_IPRG, iprX);
        break;

        /* IPRH */
    case CYGNUM_HAL_INTERRUPT_WDT_ITI:
    case CYGNUM_HAL_INTERRUPT_BSC_CMI:
        HAL_READ_UINT16(CYGARC_REG_IPRH, iprX);
        iprX &= ~CYGARC_REG_IPRH_WDT_MASK;
        iprX |= (level)*CYGARC_REG_IPRH_WDT_PRI1;
        HAL_WRITE_UINT16(CYGARC_REG_IPRH, iprX);
        break;
    case CYGNUM_HAL_INTERRUPT_IO_OEI:
        HAL_READ_UINT16(CYGARC_REG_IPRH, iprX);
        iprX &= ~CYGARC_REG_IPRH_IO_MASK;
        iprX |= (level)*CYGARC_REG_IPRH_IO_PRI1;
        HAL_WRITE_UINT16(CYGARC_REG_IPRH, iprX);
        break;


#else
# error "No hal_interrupt_update_level handling for INTC type"
#endif

    // Platform extensions
    CYGPRI_HAL_INTERRUPT_UPDATE_LEVEL_PLF(vector, level)

    default:
        CYG_FAIL("Unknown interrupt vector");
        break;
    }
}

void
hal_interrupt_set_level(int vector, int level)
{
    CYG_ASSERT((0 <= (level) && 15 >= (level)), "Illegal level");
    CYG_ASSERT((CYGNUM_HAL_ISR_MIN <= (vector)
                && CYGNUM_HAL_ISR_MAX >= (vector)), "Illegal vector");

    cyg_hal_ILVL_table[vector] = level;

    hal_interrupt_update_level(vector);
}

void
hal_interrupt_mask(int vector)
{
    switch( (vector) ) {
    case CYGNUM_HAL_INTERRUPT_NMI:
        /* fall through */
    case CYGNUM_HAL_INTERRUPT_LVL0 ... CYGNUM_HAL_INTERRUPT_LVL_MAX:
        /* Normally can only be masked by fiddling Imask in SR,
           but some platforms use external interrupt controller,
           so allow regular handling. */
        /* fall through */
#if (CYGARC_SH_MOD_INTC == 1)
    case CYGNUM_HAL_INTERRUPT_DMAC0_TE ... CYGNUM_HAL_ISR_MAX:
#elif (CYGARC_SH_MOD_INTC == 2)
    case CYGNUM_HAL_INTERRUPT_DMAC0_DEI0 ... CYGNUM_HAL_ISR_MAX:
#else
# error "Cannot unmask for INTC"
#endif
        cyg_hal_IMASK_table[vector] = 0;
        hal_interrupt_update_level(vector);
        break;
    default:
        CYG_FAIL("Unknown interrupt vector");
        break;
    }
}

void
hal_interrupt_unmask(int vector)
{
    switch( (vector) ) {
    case CYGNUM_HAL_INTERRUPT_NMI:
        /* fall through */
    case CYGNUM_HAL_INTERRUPT_LVL0 ... CYGNUM_HAL_INTERRUPT_LVL_MAX:
        /* Normally can only be masked by fiddling Imask in SR,
           but some platforms use external interrupt controller,
           so allow regular handling. */
        /* fall through */
#if (CYGARC_SH_MOD_INTC == 1)
    case CYGNUM_HAL_INTERRUPT_DMAC0_TE ... CYGNUM_HAL_ISR_MAX:
#elif (CYGARC_SH_MOD_INTC == 2)
    case CYGNUM_HAL_INTERRUPT_DMAC0_DEI0 ... CYGNUM_HAL_ISR_MAX:
#else
# error "Cannot unmask for INTC"
#endif
        cyg_hal_IMASK_table[vector] = 1;
        hal_interrupt_update_level(vector);
        break;
    default:
        CYG_FAIL("Unknown interrupt vector");
        break;
    }
}

void
hal_interrupt_acknowledge(int vector)
{
#if (CYGARC_SH_MOD_INTC == 1)
    if ( (vector) >= CYGNUM_HAL_INTERRUPT_IRQ_IRQ0
         && (vector) <= CYGNUM_HAL_INTERRUPT_IRQ_IRQ3) {

        cyg_uint8 irqcsr;

        HAL_READ_UINT8(CYGARC_REG_IRQCSR, irqcsr);
        switch ( vector ) {
#ifndef CYGHWR_HAL_SH_IRQ_USE_IRQLVL
        case CYGNUM_HAL_INTERRUPT_IRQ_IRQ0:
            irqcsr &= ~CYGARC_REG_IRQCSR_IRQ0F;
            break;
        case CYGNUM_HAL_INTERRUPT_IRQ_IRQ1:
            irqcsr &= ~CYGARC_REG_IRQCSR_IRQ1F;
            break;
        case CYGNUM_HAL_INTERRUPT_IRQ_IRQ2:
            irqcsr &= ~CYGARC_REG_IRQCSR_IRQ2F;
            break;
        case CYGNUM_HAL_INTERRUPT_IRQ_IRQ3:
            irqcsr &= ~CYGARC_REG_IRQCSR_IRQ3F;
            break;
#endif
        default:
            CYG_FAIL("Unhandled interrupt vector");
        }
        HAL_WRITE_UINT8(CYGARC_REG_IRQCSR, irqcsr);
    }
#elif (CYGARC_SH_MOD_INTC == 2)
    if ( (vector) >= CYGNUM_HAL_INTERRUPT_IRQ_IRQ0
         && (vector) <= CYGNUM_HAL_INTERRUPT_IRQ_IRQ7) {
        cyg_uint16 isr;
        cyg_uint16 mask = ~(1<<(7-(vector - CYGNUM_HAL_INTERRUPT_IRQ_IRQ0)));
        
        HAL_READ_UINT16(CYGARC_REG_ISR, isr);
        isr &= mask;
        HAL_WRITE_UINT16(CYGARC_REG_ISR, isr);
    }
#else
# error "No hal_interrupt_acknowledge code for this INTC"
#endif

    CYGPRI_HAL_INTERRUPT_ACKNOWLEDGE_PLF(vector);
}

void
hal_interrupt_configure(int vector, int level, int up)
{
#ifndef CYGHWR_HAL_SH_IRQ_USE_IRQLVL
#if (CYGARC_SH_MOD_INTC == 1)
    if ( (vector) >= CYGNUM_HAL_INTERRUPT_IRQ_IRQ0
         && (vector) <= CYGNUM_HAL_INTERRUPT_IRQ_IRQ3) {

        cyg_uint8 irqcsr, ss, mask;
        ss = 0;
        mask = CYGARC_REG_IRQCSR_IRQ_mask;
        if (level) {
            ss = CYGARC_REG_IRQCSR_IRQ_LOWLEVEL;
            CYG_ASSERT(!(up), "Cannot trigger on high level!");
        } else {
            if (up) 
                ss = CYGARC_REG_IRQCSR_IRQ_RISING;
            else
                ss = CYGARC_REG_IRQCSR_IRQ_FALLING;
        }

        switch( (vector) ) {
        case CYGNUM_HAL_INTERRUPT_IRQ_IRQ3:
            ss <<= CYGARC_REG_IRQCSR_IRQ3_shift;
            mask <<= CYGARC_REG_IRQCSR_IRQ3_shift;
            break;
        case CYGNUM_HAL_INTERRUPT_IRQ_IRQ2:
            ss <<= CYGARC_REG_IRQCSR_IRQ2_shift;
            mask <<= CYGARC_REG_IRQCSR_IRQ2_shift;
            break;
        case CYGNUM_HAL_INTERRUPT_IRQ_IRQ1:
            ss <<= CYGARC_REG_IRQCSR_IRQ1_shift;
            mask <<= CYGARC_REG_IRQCSR_IRQ1_shift;
            break;
        case CYGNUM_HAL_INTERRUPT_IRQ_IRQ0:
            ss <<= CYGARC_REG_IRQCSR_IRQ0_shift;
            mask <<= CYGARC_REG_IRQCSR_IRQ0_shift;
            break;
        default:
            CYG_FAIL("Unhandled interrupt vector");
        }

        HAL_READ_UINT8(CYGARC_REG_IRQCSR, irqcsr);
        irqcsr &= ~mask;
        irqcsr |= ss;
        HAL_WRITE_UINT8(CYGARC_REG_IRQCSR, irqcsr);
    }
#endif
#endif

    CYGPRI_HAL_INTERRUPT_CONFIGURE_PLF(vector, level, up);
}

//---------------------------------------------------------------------------
void
hal_variant_init(void)
{
    HAL_CLOCK_VAR_INITIALIZE(CYGNUM_HAL_RTC_PERIOD);

    hal_interrupt_set_vectors();
}

//---------------------------------------------------------------------------
// Low-level delay (in microseconds)

#ifdef CYGARC_SH_MOD_FRT
void
hal_delay_us(int usecs)
{
    cyg_uint16 val1, val2;
    cyg_int32 diff, clocks, wrap;

    /* Read compare A register */
    HAL_WRITE_UINT8(CYGARC_REG_TOCR, CYGARC_REG_TOCR_OLVLA);
    HAL_READ_UINT16(CYGARC_REG_OCR, val1);
    wrap = (cyg_int32)val1;

    clocks = CYGHWR_HAL_SH_ONCHIP_PERIPHERAL_SPEED/CYGHWR_HAL_SH_RTC_PRESCALE/1000*usecs/1000;

    HAL_READ_UINT16(CYGARC_REG_FRC, val1);
    while (clocks > 0) {
        HAL_READ_UINT16(CYGARC_REG_FRC, val2);

        diff = (cyg_int32)val1 - (cyg_int32)val2;
        if (diff > 0)
            clocks += (diff-wrap);
        else
            clocks += diff;

        val1 = val2;
    }
}
#elif defined(CYGARC_SH_MOD_CMT)
void
hal_delay_us(int usecs)
{
    cyg_uint16 val1, val2;
    cyg_int32 diff, clocks, wrap;

    /* Read compare 0 register */
    HAL_READ_UINT16(CYGARC_REG_CMCOR0, val1);
    wrap = (cyg_int32)val1;

    clocks = CYGHWR_HAL_SH_ONCHIP_PERIPHERAL_SPEED/CYGHWR_HAL_SH_RTC_PRESCALE/1000*usecs/1000;

    HAL_READ_UINT16(CYGARC_REG_CMCNT0, val1);
    while (clocks > 0) {
        HAL_READ_UINT16(CYGARC_REG_CMCNT0, val2);

        diff = (cyg_int32)val1 - (cyg_int32)val2;
        if (diff > 0)
            clocks += (diff-wrap);
        else
            clocks += diff;

        val1 = val2;
    }
}
#else
# error "No hal_delay_us implementation"
#endif


//---------------------------------------------------------------------------
// End of hal_misc.c