quicc2_scc_serial.c

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//==========================================================================
//
//      io/serial/powerpc/quicc2_scc_serial.c
//
//      PowerPC QUICC2 (SCC) Serial I/O Interface Module (interrupt driven)
//
//==========================================================================
//####ECOSGPLCOPYRIGHTBEGIN####
// -------------------------------------------
// This file is part of eCos, the Embedded Configurable Operating System.
// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
// Copyright (C) 2002 Gary Thomas
//
// eCos is free software; you can redistribute it and/or modify it under
// the terms of the GNU General Public License as published by the Free
// Software Foundation; either version 2 or (at your option) any later version.
//
// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or
// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
// for more details.
//
// You should have received a copy of the GNU General Public License along
// with eCos; if not, write to the Free Software Foundation, Inc.,
// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
//
// As a special exception, if other files instantiate templates or use macros
// or inline functions from this file, or you compile this file and link it
// with other works to produce a work based on this file, this file does not
// by itself cause the resulting work to be covered by the GNU General Public
// License. However the source code for this file must still be made available
// in accordance with section (3) of the GNU General Public License.
//
// This exception does not invalidate any other reasons why a work based on
// this file might be covered by the GNU General Public License.
//
// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
// at http://sources.redhat.com/ecos/ecos-license/
// -------------------------------------------
//####ECOSGPLCOPYRIGHTEND####
//==========================================================================
//#####DESCRIPTIONBEGIN####
//
// Author(s):    mtek
// Contributors: gthomas
// Date:         1999-06-20
// Purpose:      QUICC2 SCC Serial I/O module (interrupt driven version)
// Description: 
//
//####DESCRIPTIONEND####
//
//==========================================================================

#include <pkgconf/system.h>
#include <pkgconf/io_serial.h>
#include <pkgconf/io.h>
#include <cyg/io/io.h>
#include <cyg/hal/hal_intr.h>
#include <cyg/hal/var_intr.h>
#include <cyg/io/devtab.h>
#include <cyg/io/serial.h>
#include <cyg/infra/diag.h>
#include <cyg/hal/hal_cache.h>
#include <cyg/hal/mpc8260.h>
#include CYGBLD_HAL_PLATFORM_H

#include "quicc2_scc_serial.h"
#define QUICC2_VADS_IMM_BASE    0x04700000
#define QUICC2_VADS_BCSR_BASE   0x04500000

#ifdef CYGPKG_IO_SERIAL_POWERPC_QUICC2_SCC

static bool 
quicc2_scc_serial_init(struct cyg_devtab_entry *tab);
static bool 
quicc2_scc_serial_putc(serial_channel *chan, 
                       unsigned char c);
static Cyg_ErrNo 
quicc2_scc_serial_lookup(struct cyg_devtab_entry **tab, 
                         struct cyg_devtab_entry *sub_tab,
                         const char *name);
static unsigned char 
quicc2_scc_serial_getc(serial_channel *chan);
static Cyg_ErrNo 
quicc2_scc_serial_set_config(serial_channel *chan,
                             cyg_uint32 key, const void *xbuf,
                             cyg_uint32 *len);
static void 
quicc2_scc_serial_start_xmit(serial_channel *chan);
static void 
quicc2_scc_serial_stop_xmit(serial_channel *chan);

static cyg_uint32 
quicc2_scc_serial_ISR(cyg_vector_t vector, 
                      cyg_addrword_t data);
static void       
quicc2_scc_serial_DSR(cyg_vector_t vector, 
                      cyg_ucount32 count, 
                      cyg_addrword_t data);

static SERIAL_FUNS(quicc2_scc_serial_funs, 
                   quicc2_scc_serial_putc, 
                   quicc2_scc_serial_getc,
                   quicc2_scc_serial_set_config,
                   quicc2_scc_serial_start_xmit,
                   quicc2_scc_serial_stop_xmit
    );

#ifdef CYGPKG_IO_SERIAL_POWERPC_QUICC2_SCC_SCC1
static quicc2_scc_serial_info quicc2_scc_serial_info1;

#if CYGNUM_IO_SERIAL_POWERPC_QUICC2_SCC_SCC1_BUFSIZE > 0
static unsigned char quicc2_scc_serial_out_buf1[CYGNUM_IO_SERIAL_POWERPC_QUICC2_SCC_SCC1_BUFSIZE];
static unsigned char quicc2_scc_serial_in_buf1[CYGNUM_IO_SERIAL_POWERPC_QUICC2_SCC_SCC1_BUFSIZE];

static SERIAL_CHANNEL_USING_INTERRUPTS(quicc2_scc_serial_channel1,
                                       quicc2_scc_serial_funs, 
                                       quicc2_scc_serial_info1,
                                       CYG_SERIAL_BAUD_RATE(CYGNUM_IO_SERIAL_POWERPC_QUICC2_SCC_SCC1_BAUD),
                                       CYG_SERIAL_STOP_DEFAULT,
                                       CYG_SERIAL_PARITY_DEFAULT,
                                       CYG_SERIAL_WORD_LENGTH_DEFAULT,
                                       CYG_SERIAL_FLAGS_DEFAULT,
                                       &quicc2_scc_serial_out_buf1[0], sizeof(quicc2_scc_serial_out_buf1),
                                       &quicc2_scc_serial_in_buf1[0], sizeof(quicc2_scc_serial_in_buf1)
    );
#else
static SERIAL_CHANNEL(quicc2_scc_serial_channel1,
                      quicc2_scc_serial_funs, 
                      quicc2_scc_serial_info1,
                      CYG_SERIAL_BAUD_RATE(CYGNUM_IO_SERIAL_POWERPC_QUICC2_SCC_SCC1_BAUD),
                      CYG_SERIAL_STOP_DEFAULT,
                      CYG_SERIAL_PARITY_DEFAULT,
                      CYG_SERIAL_WORD_LENGTH_DEFAULT,
                      CYG_SERIAL_FLAGS_DEFAULT
    );
#endif

static unsigned char quicc2_scc1_txbuf[CYGNUM_IO_SERIAL_POWERPC_QUICC2_SCC_SCC1_TxNUM]
                                      [CYGNUM_IO_SERIAL_POWERPC_QUICC2_SCC_SCC1_TxSIZE + HAL_DCACHE_LINE_SIZE-1];
static unsigned char quicc2_scc1_rxbuf[CYGNUM_IO_SERIAL_POWERPC_QUICC2_SCC_SCC1_RxNUM]
                                      [CYGNUM_IO_SERIAL_POWERPC_QUICC2_SCC_SCC1_RxSIZE + HAL_DCACHE_LINE_SIZE-1];

DEVTAB_ENTRY(quicc2_scc_serial_io1, 
             CYGDAT_IO_SERIAL_POWERPC_QUICC2_SCC_SCC1_NAME,
             0,                     // Does not depend on a lower level interface
             &cyg_io_serial_devio, 
             quicc2_scc_serial_init, 
             quicc2_scc_serial_lookup,     // Serial driver may need initializing
             &quicc2_scc_serial_channel1
    );
#endif //  CYGPKG_IO_SERIAL_POWERPC_QUICC2_SCC_SCC1

#ifdef CYGPKG_IO_SERIAL_POWERPC_QUICC2_SCC_SCC2
static quicc2_scc_serial_info quicc2_scc_serial_info2;

#if CYGNUM_IO_SERIAL_POWERPC_QUICC2_SCC_SCC2_BUFSIZE > 0
static unsigned char quicc2_scc_serial_out_buf2[CYGNUM_IO_SERIAL_POWERPC_QUICC2_SCC_SCC2_BUFSIZE];
static unsigned char quicc2_scc_serial_in_buf2[CYGNUM_IO_SERIAL_POWERPC_QUICC2_SCC_SCC2_BUFSIZE];

static SERIAL_CHANNEL_USING_INTERRUPTS(quicc2_scc_serial_channel2,
                                       quicc2_scc_serial_funs, 
                                       quicc2_scc_serial_info2,
                                       CYG_SERIAL_BAUD_RATE(CYGNUM_IO_SERIAL_POWERPC_QUICC2_SCC_SCC2_BAUD),
                                       CYG_SERIAL_STOP_DEFAULT,
                                       CYG_SERIAL_PARITY_DEFAULT,
                                       CYG_SERIAL_WORD_LENGTH_DEFAULT,
                                       CYG_SERIAL_FLAGS_DEFAULT,
                                       &quicc2_scc_serial_out_buf2[0], sizeof(quicc2_scc_serial_out_buf2),
                                       &quicc2_scc_serial_in_buf2[0], sizeof(quicc2_scc_serial_in_buf2)
    );
#else
static SERIAL_CHANNEL(quicc2_scc_serial_channel2,
                      quicc2_scc_serial_funs, 
                      quicc2_scc_serial_info2,
                      CYG_SERIAL_BAUD_RATE(CYGNUM_IO_SERIAL_POWERPC_QUICC2_SCC_SCC2_BAUD),
                      CYG_SERIAL_STOP_DEFAULT,
                      CYG_SERIAL_PARITY_DEFAULT,
                      CYG_SERIAL_WORD_LENGTH_DEFAULT,
                      CYG_SERIAL_FLAGS_DEFAULT
    );
#endif
static unsigned char quicc2_scc2_txbuf[CYGNUM_IO_SERIAL_POWERPC_QUICC2_SCC_SCC2_TxNUM]
                                      [CYGNUM_IO_SERIAL_POWERPC_QUICC2_SCC_SCC2_TxSIZE + HAL_DCACHE_LINE_SIZE-1];
static unsigned char quicc2_scc2_rxbuf[CYGNUM_IO_SERIAL_POWERPC_QUICC2_SCC_SCC2_RxNUM]
                                      [CYGNUM_IO_SERIAL_POWERPC_QUICC2_SCC_SCC2_RxSIZE + HAL_DCACHE_LINE_SIZE-1];

DEVTAB_ENTRY(quicc2_scc_serial_io2, 
             CYGDAT_IO_SERIAL_POWERPC_QUICC2_SCC_SCC2_NAME,
             0,                     // Does not depend on a lower level interface
             &cyg_io_serial_devio, 
             quicc2_scc_serial_init, 
             quicc2_scc_serial_lookup,     // Serial driver may need initializing
             &quicc2_scc_serial_channel2
    );
#endif //  CYGPKG_IO_SERIAL_POWERPC_QUICC2_SCC

#ifdef CYGDBG_DIAG_BUF
extern int enable_diag_uart;
#endif // CYGDBG_DIAG_BUF

// Internal function to actually configure the hardware to 
// desired baud rate, stop bits and parity ...
static bool
quicc2_scc_serial_config_port(serial_channel *chan, 
                              cyg_serial_info_t *new_config, 
                              bool init)
{
    quicc2_scc_serial_info *scc_chan = (quicc2_scc_serial_info *)chan->dev_priv;
    volatile t_PQ2IMM *IMM = (volatile t_PQ2IMM *) QUICC2_VADS_IMM_BASE;

    unsigned long b_rate   = select_baud[new_config->baud];

    if (b_rate == 0) return false;

    // Stop the transmitter while changing baud rate
    while (IMM->cpm_cpcr & QUICC2_CPCR_READY);
    IMM->cpm_cpcr = scc_chan->scc_cpcr | QUICC2_CPCR_STOP_TX | QUICC2_CPCR_READY;
    while (IMM->cpm_cpcr & QUICC2_CPCR_READY);

    // Disable Tx, RX and put them in a reset state
    scc_chan->scc_regs->gsmr_l &= ~(QUICC2_SCC_GSMR_L_ENT | QUICC2_SCC_GSMR_L_ENR);

    // Set the baud rate
    *(scc_chan->brg) = (UART_BIT_RATE(b_rate) << 1) | QUICC2_BRG_EN;

    // Set stop bits, word length and parity
    scc_chan->scc_regs->psmr = QUICC2_SCC_PSMR_ASYNC |
      select_stop_bits[new_config->stop] |
      select_word_length[new_config->word_length - CYGNUM_SERIAL_WORD_LENGTH_5] | 
      select_parity[new_config->parity];

    // Support fractional stop bits 
    scc_chan->scc_regs->dsr = (new_config->stop & 1) ? QUICC2_SCC_DSR_FULL : QUICC2_SCC_DSR_HALF;
      
    // Initialize the parameters
    while (IMM->cpm_cpcr & QUICC2_CPCR_READY);
    IMM->cpm_cpcr = scc_chan->scc_cpcr | QUICC2_CPCR_INIT_TX_RX | QUICC2_CPCR_READY;
    while (IMM->cpm_cpcr & QUICC2_CPCR_READY);

    // Enable Tx and Rx
    scc_chan->scc_regs->gsmr_l |= (QUICC2_SCC_GSMR_L_ENT | QUICC2_SCC_GSMR_L_ENR);

    if (new_config != &chan->config) {
        chan->config = *new_config;
    }
    return true;
}

// Function to set up internal tables for device.
static void
quicc2_scc_serial_init_info(quicc2_scc_serial_info *scc_chan,
                            int SCC_index,
                            int BRG_index,
                            int TxBD, int TxNUM, int TxSIZE,
                            cyg_uint8 *TxBUF,
                            int RxBD, int RxNUM, int RxSIZE,
                            cyg_uint8 *RxBUF)
{
  volatile t_PQ2IMM *IMM = (volatile t_PQ2IMM *) QUICC2_VADS_IMM_BASE;
#ifdef CYGPKG_HAL_POWERPC_VADS
  volatile t_BCSR *bcsr  = (volatile t_BCSR *) QUICC2_VADS_BCSR_BASE;
#endif
  t_UartScc_Pram *uart_pram;
  scc_bd  *txbd, *rxbd;
  int i;
  
  // Disable the channel, just in case 
  IMM->scc_regs[SCC_index-1].gsmr_l &= ~(QUICC2_SCC_GSMR_L_ENT | QUICC2_SCC_GSMR_L_ENR);
  
  switch (SCC_index) {
    
  case 1:
    // Put the data into the info structure 
    scc_chan->scc_cpcr = QUICC2_CPCR_SCC1;
    scc_chan->scc_regs = &(IMM->scc_regs[0]);
    scc_chan->scc_pram = &(IMM->pram.serials.scc_pram[0]);
    scc_chan->int_vector = CYGNUM_HAL_INTERRUPT_SCC1;
    
    // Set-up the PORT D pins
    IMM->io_regs[PORT_D].psor &= ~QUICC2_SCC1_PORTD_PPAR;
    IMM->io_regs[PORT_D].psor |=  QUICC2_SCC1_PORTD_PDIR;
    IMM->io_regs[PORT_D].ppar |=  QUICC2_SCC1_PORTD_PPAR;
    IMM->io_regs[PORT_D].pdir &= ~QUICC2_SCC1_PORTD_PPAR;