if_i21143.c
来自「eCos操作系统源码」· C语言 代码 · 共 1,953 行 · 第 1/5 页
C
1,953 行
v = mii_read_register( ioaddr, i ); diag_printf( "MII/PHY register %2x%c = %04x\n", i, 'h', v ); } if ( ETH & which ) for ( i = 0; i < 16; i++ ) { cyg_uint32 v; v = INL( (ioaddr + (i << 3)) ); diag_printf( "21143 register CSR%2d (at %2x%c) = %08x\n", i, (i << 3), 'h', v ); }}#endif// ------------------------------------------------------------------------//// REGISTERS (CSRs) and THEIR BITS//// ------------------------------------------------------------------------// All registers are 32bit entities on 64bit boundaries.#define CSR0 (ioaddr + ( 0 << 3))#define CSR1 (ioaddr + ( 1 << 3))#define CSR2 (ioaddr + ( 2 << 3))#define CSR3 (ioaddr + ( 3 << 3))#define CSR4 (ioaddr + ( 4 << 3))#define CSR5 (ioaddr + ( 5 << 3))#define CSR6 (ioaddr + ( 6 << 3))#define CSR7 (ioaddr + ( 7 << 3))#define CSR8 (ioaddr + ( 8 << 3))#define CSR9 (ioaddr + ( 9 << 3))#define CSR10 (ioaddr + (10 << 3))#define CSR11 (ioaddr + (11 << 3))#define CSR12 (ioaddr + (12 << 3))#define CSR13 (ioaddr + (13 << 3))#define CSR14 (ioaddr + (14 << 3))#define CSR15 (ioaddr + (15 << 3))#define CSR1_PM CSR1#define CSR2_PM CSR2#define CSR_BUSMODE CSR0 #define CSR_TXPOLL CSR1 #define CSR_RXPOLL CSR2 #define CSR_RXBASE CSR3 #define CSR_TXBASE CSR4 #define CSR_STATUS CSR5 #define CSR_OPMODE CSR6 #define CSR_INTR_ENABLE CSR7 #define CSR_MISS_OFL_COUNT CSR8 #define CSR_ROM_MII_MGT CSR9 #define CSR_ROM_PGM_ADDR CSR10#define CSR_INTR_MITIGATION CSR11#define CSR_SIA_STATUS CSR12#define CSR_SIA_CONN CSR13#define CSR_SIA_TXRX CSR14#define CSR_SIA_GPPORT CSR15#define CSR_WUFILTER CSR1_PM#define CSR_WUEVENTS CSR2_PM// -------- BUSMODE#define CSR_BUSMODE_PM (1<<26)#define CSR_BUSMODE_WIE (1<<24)#define CSR_BUSMODE_RLE (1<<23)#define CSR_BUSMODE_RME (1<<21)#define CSR_BUSMODE_DBO_BE (1<<20)#define CSR_BUSMODE_DBO_LE ( 0 )#define CSR_BUSMODE_TAP_SHIFT (17)#define CSR_BUSMODE_CAL_SHIFT (14)#define CSR_BUSMODE_PBL_SHIFT ( 8)#define CSR_BUSMODE_ENDIAN_BE (1<< 7)#define CSR_BUSMODE_ENDIAN_LE ( 0 )#define CSR_BUSMODE_DSL_SHIFT ( 2)#define CSR_BUSMODE_BAR (1<< 1)#define CSR_BUSMODE_RESET (1<< 0)// -------- STATUS#define CSR_STATUS_LC (1<<27)#define CSR_STATUS_GPI (1<<26)#define CSR_STATUS_EB (7 << 23)#define CSR_STATUS_TXSTATUS (7 << 20)#define CSR_STATUS_TXSTATUS_STOPPED (0 << 20)#define CSR_STATUS_TXSTATUS_SUSPENDED (6 << 20)#define CSR_STATUS_RXSTATUS (7 << 17)#define CSR_STATUS_RXSTATUS_STOPPED (0 << 17)#define CSR_STATUS_RXSTATUS_SUSPENDED (4 << 17)#define CSR_STATUS_NIS (1<<16)#define CSR_STATUS_AIS (1<<15)#define CSR_STATUS_ERI (1<<14)#define CSR_STATUS_FBE (1<<13)#define CSR_STATUS_LNF (1<<12)#define CSR_STATUS_GTE (1<<11)#define CSR_STATUS_ETI (1<<10)#define CSR_STATUS_RWT (1<< 9)#define CSR_STATUS_RX_STOPPED (1<< 8)#define CSR_STATUS_RBU (1<< 7)#define CSR_STATUS_RX_INTR (1<< 6)#define CSR_STATUS_UNF (1<< 5)#define CSR_STATUS_LNP_ANC (1<< 4)#define CSR_STATUS_TJT (1<< 3)#define CSR_STATUS_TBU (1<< 2)#define CSR_STATUS_TX_STOPPED (1<< 1)#define CSR_STATUS_TX_INTR (1<< 0)// -------- OPMODE#define CSR_OPMODE_SC (1<<31)#define CSR_OPMODE_RA (1<<30)#define CSR_OPMODE_IGNOREMSB (1<<26)#define CSR_OPMODE_MUST_BE_ONE (1<<25)#define CSR_OPMODE_SCR (1<<24)#define CSR_OPMODE_PCS (1<<23)#define CSR_OPMODE_TTM (1<<22)#define CSR_OPMODE_SF (1<<21)#define CSR_OPMODE_HBD (1<<19)#define CSR_OPMODE_PS (1<<18)#define CSR_OPMODE_PS_MIISYM (1<<18)#define CSR_OPMODE_CA (1<<17)#define CSR_OPMODE_TX_THRES_SHIFT (14)#define CSR_OPMODE_TX_START (1<<13)#define CSR_OPMODE_FC (1<<12)#define CSR_OPMODE_LOOPBACK_SHIFT (10)#define CSR_OPMODE_FD (1<< 9)#define CSR_OPMODE_MULTICAST (1<< 7)#define CSR_OPMODE_PROMISC (1<< 6)#define CSR_OPMODE_SB (1<< 5)#define CSR_OPMODE_IF (1<< 4)#define CSR_OPMODE_PB (1<< 3)#define CSR_OPMODE_HO (1<< 2)#define CSR_OPMODE_RX_START (1<< 1)#define CSR_OPMODE_HP (1<< 0)// -------- INTR_ENABLE// uses the same bits as STATUS, hurrah!// -------- MISS_OFL_COUNT#define CSR_MISS_OFL_COUNT_NO_RXBUFS_MASK (0x0001ffff)#define CSR_MISS_OFL_COUNT_NO_RXBUFS_SHIFT ( 0)#define CSR_MISS_OFL_COUNT_NO_RXFIFO_MASK (0x1ffe0000)#define CSR_MISS_OFL_COUNT_NO_RXFIFO_SHIFT (17)// -------- ROM_MII_MGT#define CSR_ROM_MII_MGT_MDI (1<<19)#define CSR_ROM_MII_MGT_MOM (1<<18)#define CSR_ROM_MII_MGT_MOM_READ (1<<18)#define CSR_ROM_MII_MGT_MDO (1<<17)#define CSR_ROM_MII_MGT_MDC (1<<16)#define CSR_ROM_MII_MGT_RD (1<<14)#define CSR_ROM_MII_MGT_WR (1<<13)#define CSR_ROM_MII_MGT_BR (1<<12)#define CSR_ROM_MII_MGT_SR (1<<11)#define CSR_ROM_MII_MGT_REG (1<<10)#define CSR_ROM_MII_MGT_SR_DO (1<< 3)#define CSR_ROM_MII_MGT_SR_DI (1<< 2)#define CSR_ROM_MII_MGT_SR_CK (1<< 1)#define CSR_ROM_MII_MGT_SR_CS (1<< 0)#define CSR_ROM_MII_MGT_DATA (0xff)// -------- SIA defaults#define CSR_SIA_CONN_DEFAULT (0)#define CSR_SIA_TXRX_DEFAULT (0)#define CSR_SIA_GPPORT_DEFAULT (8)// ------------------------------------------------------------------------//// RECEIVE/TRANSMIT FRAME DESCRIPTORS//// ------------------------------------------------------------------------//#if (CYG_BYTEORDER == CYG_MSBFIRST)// Common to both Rx and Tx DES0#define DES0_STATUS_OWN (1<<31)#define DES0_STATUS_OWN_DONE (0<<31)#define DES0_STATUS_OWN_OPEN (1<<31)#define DES0_STATUS_ERROR (1<<15)// Rx specific results:#define RDES0_STATUS_FF (1<<30)#define RDES0_STATUS_DE (1<<14)#define RDES0_STATUS_RF (1<<11)#define RDES0_STATUS_MF (1<<10)#define RDES0_STATUS_FIRST (1<< 9)#define RDES0_STATUS_LAST (1<< 8)#define RDES0_STATUS_TOOLONG (1<< 7)#define RDES0_STATUS_LATECOLL (1<< 6)#define RDES0_STATUS_FT (1<< 5)#define RDES0_STATUS_RW (1<< 4)#define RDES0_STATUS_RE (1<< 3)#define RDES0_STATUS_DB (1<< 2)#define RDES0_STATUS_CRC (1<< 1)#define RDES0_STATUS_ZERO (1<< 0)#define RDES0_COUNT_MASK (0x3fff0000) #define RDES0_COUNT_SHIFT ( 16 ) // Tx specific results:#define TDES0_STATUS_TJTO (1<<14)#define TDES0_STATUS_LO (1<<11)#define TDES0_STATUS_NC (1<<10)#define TDES0_STATUS_LC (1<< 9)#define TDES0_STATUS_EC (1<< 8)#define TDES0_STATUS_HF (1<< 7)#define TDES0_STATUS_LF (1<< 2)#define TDES0_STATUS_UFL (1<< 1)#define TDES0_STATUS_DE (1<< 0)#define TDES0_STATUS_CC_MASK (0x78) #define TDES0_STATUS_CC_SHIFT ( 3 )// Common to both Rx and Tx DES1#define DES1_ENDRING (1<<25)#define DES1_2ACHAIN (1<<24)#define DES1_B2SIZE_MASK (0x7ff << 11)#define DES1_B2SIZE_SHIFT (11)#define DES1_B1SIZE_MASK (0x7ff)#define DES1_B1SIZE_SHIFT (0)// Rx DES1 has no special bits - Rx descriptors have no "controls"// Tx specific controls in DES1:#define TDES1_CONTROL_INTERRUPT (1<<31)#define TDES1_CONTROL_LAST (1<<30)#define TDES1_CONTROL_FIRST (1<<29)#define TDES1_CONTROL_SETUP_FT1 (1<<28)#define TDES1_CONTROL_SETUP (1<<27)#define TDES1_CONTROL_NO_CRC (1<<26)#define TDES1_CONTROL_NO_PAD (1<<23)#define TDES1_CONTROL_SETUP_FT0 (1<<22)// ------------------------------------------------------------------------//// PHY common constants - registers are read over MII.// // I don't know how much they have in common, but I think MII is pretty// standard, and the "mandated" registers ought to be common.#define PHY_CONTROL_REG (0)#define PHY_STATUS_REG (1)#define PHY_ID_ONE (2)#define PHY_ID_TWO (3)#define PHY_AUTONEG_ADVERT (4)#define PHY_AUTONEG_REMOTE (5)#define PHY_CONTROL_RESET (1<<15)#define PHY_CONTROL_LOOPBACK (1<<14)#define PHY_CONTROL_SPEED100 (1<<13)#define PHY_CONTROL_AUTONEG_EN (1<<12)#define PHY_CONTROL_POWERDOWN (1<<11)#define PHY_CONTROL_MII_DIS (1<<10)#define PHY_CONTROL_AUTONEG_RST (1<< 9)#define PHY_CONTROL_DPLX_FULL (1<< 8)#define PHY_CONTROL_COLLTEST (1<< 7) #define PHY_STATUS_CAP_T4 (1<<15)#define PHY_STATUS_CAP_100TXF (1<<14)#define PHY_STATUS_CAP_100TXH (1<<13)#define PHY_STATUS_CAP_10TF (1<<12)#define PHY_STATUS_CAP_10TH (1<<11)#define PHY_STATUS_CAP_SUPR (1<< 6)#define PHY_STATUS_AUTONEG_ACK (1<< 5)#define PHY_STATUS_REMOTEFAULT (1<< 4)#define PHY_STATUS_CAP_AUTONEG (1<< 3)#define PHY_STATUS_LINK_OK (1<< 2)#define PHY_STATUS_JABBER (1<< 1)#define PHY_STATUS_EXTREGS (1<< 0)// These are the same for both AUTONEG registers#define PHY_AUTONEG_NEXT (1<<15)#define PHY_AUTONEG_ACK (1<<14)#define PHY_AUTONEG_REMOTEFAULT (1<<13)#define PHY_AUTONEG_100BASET4 (1<< 9)#define PHY_AUTONEG_100BASETX_FDX (1<< 8)#define PHY_AUTONEG_100BASETX_HDX (1<< 7)#define PHY_AUTONEG_10BASET_FDX (1<< 6)#define PHY_AUTONEG_10BASET_HDX (1<< 5)#define PHY_AUTONEG_CSMA_802_3 (1<< 0)// ------------------------------------------------------------------------//// DEVICES AND PACKET QUEUES//// ------------------------------------------------------------------------// Use arrays provided by platform header to verify pointers.#ifdef CYGDBG_USE_ASSERTS#define CHECK_NDP_SC_LINK() \ CYG_MACRO_START \ int zzz, valid_netdev = 0, valid_sc = 0; \ for(zzz = 0; zzz < CYGNUM_DEVS_ETH_INTEL_I21143_DEV_COUNT; zzz++) { \ if (i21143_netdev_array[zzz] == ndp) valid_netdev = 1; \ if (i21143_sc_array[zzz] == sc) valid_sc = 1; \ if (valid_sc || valid_netdev) break; \ } \ CYG_ASSERT( valid_netdev, "Bad ndp" ); \ CYG_ASSERT( valid_sc, "Bad sc" ); \ CYG_ASSERT( (void *)p_i21143 == i21143_sc_array[zzz]->driver_private, \ "sc pointer bad" ); \ CYG_MACRO_END#else#define CHECK_NDP_SC_LINK()#endif#define IF_BAD_21143( _p_ ) \if (({ \ int zzz, valid_p = 0; \ for(zzz = 0; zzz < CYGNUM_DEVS_ETH_INTEL_I21143_DEV_COUNT; zzz++) { \ if (i21143_priv_array[zzz] == (_p_)) { \ valid_p = 1; \ break; \ } \ } \ CYG_ASSERT(valid_p, "Bad pointer-to-i21143"); \ (!valid_p); \}))#if defined( DEBUG_TRAFFIC_TXDETAILS ) || defined( DEBUG_MAC )static void dump_tx_details( struct i21143 *p_i21143, char *s ){ int i; cyg_uint32 prev = 0x0f0f0f0f; for ( i = 0; i < TX_DESCRIPTORS ; i++ ) { if ( 0 != (p_i21143->tx_ring[i].des1 | p_i21143->tx_ring[i].buf1 | p_i21143->tx_ring[i].buf2) || ((p_i21143->tx_ring[i].des0 != prev ) ) ) { prev = p_i21143->tx_ring[i].des0; diag_printf( "%10s: bd[%2d] = %08x %08x %8x %x", s, i, p_i21143->tx_ring[i].des0, p_i21143->tx_ring[i].des1, p_i21143->tx_ring[i].buf1, p_i21143->tx_ring[i].buf2 ); diag_printf( " %s, %s%s %s\n", p_i21143->tx_ring[i].des0 & DES0_STATUS_OWN_OPEN ? "Open" : "Done" , p_i21143->tx_ring[i].des1 & TDES1_CONTROL_FIRST ? "First" : "" , p_i21143->tx_ring[i].des1 & TDES1_CONTROL_LAST ? "Last" : "" , p_i21143->tx_ring[i].des1 & TDES1_CONTROL_INTERRUPT ? "Interrupt" : "" ); } }}#endif// ------------------------------------------------------------------------//// NETWORK INTERFACE INITIALIZATION//// Function : i21143_init//// Description :// This routine resets, configures, and initializes the chip.//// ------------------------------------------------------------------------static booli21143_init(struct cyg_netdevtab_entry * ndp){ static int initialized = 0; // only probe PCI et al *once* struct eth_drv_sc *sc; struct i21143 *p_i21143; cyg_uint8 mac_address[ETHER_ADDR_LEN];#ifdef DEBUG diag_printf("intel_i21143_init\n");#endif sc = (struct eth_drv_sc *)(ndp->device_instance); p_i21143 = (struct i21143 *)(sc->driver_private); IF_BAD_21143( p_i21143 ) {#ifdef DEBUG diag_printf( "Bad device private pointer %x\n", sc->driver_private );#endif return 0; } CHECK_NDP_SC_LINK(); p_i21143->ndp = (void *)ndp; if ( 0 == initialized++ ) { // then this is the first time ever: if ( ! pci_init_find_21143s() ) {#ifdef DEBUG⌨️ 快捷键说明
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