if_fec.c

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//==========================================================================
//
//      dev/if_fec.c
//
//      Fast ethernet device driver for PowerPC MPC8260 boards
//
//==========================================================================
//####ECOSGPLCOPYRIGHTBEGIN####
// -------------------------------------------
// This file is part of eCos, the Embedded Configurable Operating System.
// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
// Copyright (C) 2002 Gary Thomas
//
// eCos is free software; you can redistribute it and/or modify it under
// the terms of the GNU General Public License as published by the Free
// Software Foundation; either version 2 or (at your option) any later version.
//
// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or
// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
// for more details.
//
// You should have received a copy of the GNU General Public License along
// with eCos; if not, write to the Free Software Foundation, Inc.,
// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
//
// As a special exception, if other files instantiate templates or use macros
// or inline functions from this file, or you compile this file and link it
// with other works to produce a work based on this file, this file does not
// by itself cause the resulting work to be covered by the GNU General Public
// License. However the source code for this file must still be made available
// in accordance with section (3) of the GNU General Public License.
//
// This exception does not invalidate any other reasons why a work based on
// this file might be covered by the GNU General Public License.
//
// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
// at http://sources.redhat.com/ecos/ecos-license/
// -------------------------------------------
//####ECOSGPLCOPYRIGHTEND####
//==========================================================================
//#####DESCRIPTIONBEGIN####
//
// Author(s):    mtek
// Contributors: pfine
// Date:         2002-02-20
// Purpose:      
// Description:  hardware driver for MPC8260 FEC
//              
//
//####DESCRIPTIONEND####
//
//==========================================================================

#include <pkgconf/devs_eth_powerpc_quicc2.h>
#include <cyg/infra/cyg_type.h>
#include <cyg/infra/diag.h>

#include <cyg/hal/hal_arch.h>
#include <cyg/hal/hal_cache.h>
#include <cyg/hal/hal_intr.h>
#include <cyg/hal/var_intr.h>
#include <cyg/hal/drv_api.h>
#include <cyg/hal/hal_if.h>
#include <cyg/hal/mpc8260.h>

#include <cyg/io/eth/netdev.h>
#include <cyg/io/eth/eth_drv.h>

#ifdef CYGPKG_NET
#include <pkgconf/net.h>
#endif

#include "fec.h"
#include "EnetPHY.h"

#define ALIGN_TO_CACHE_LINES(x)  ( (long)((x) + 31) & 0xffffffe0 )

static unsigned char fec_eth_rxbufs[CYGNUM_DEVS_ETH_POWERPC_QUICC2_RxNUM *
                                    (CYGNUM_DEVS_ETH_POWERPC_QUICC2_BUFSIZE + 32)];
static unsigned char fec_eth_txbufs[CYGNUM_DEVS_ETH_POWERPC_QUICC2_TxNUM *
                                    (CYGNUM_DEVS_ETH_POWERPC_QUICC2_BUFSIZE + 32)];

// Buffer descriptors are in dual ported RAM, which is marked non-cached
#define FEC_BDs_NONCACHED
static struct fec_bd *const fec_eth_rxring = (struct fec_bd *) 
  (QUICC2_VADS_IMM_BASE + FEC_PRAM_RxBD_Base);
static struct fec_bd *const fec_eth_txring = (struct fec_bd *) 
  (QUICC2_VADS_IMM_BASE + FEC_PRAM_TxBD_Base);

static struct fec_eth_info fec_eth0_info;

static unsigned short _default_enaddr[] = {0x1234, 0x5678, 0x90a1};
static unsigned char enaddr[6];

#ifdef CYGPKG_REDBOOT
#include <pkgconf/redboot.h>
#ifdef CYGSEM_REDBOOT_FLASH_CONFIG
#include <redboot.h>
#include <flash_config.h>
RedBoot_config_option("Network hardware address [MAC]",
                      fec_esa,
                      ALWAYS_ENABLED, true,
                      CONFIG_ESA, 0
    );
RedBoot_config_option("Attempt to find 100 Mbps Ethernet",
                      fec_100,
                      ALWAYS_ENABLED, true,
                      CONFIG_BOOL, 0
    );
#endif
#endif

#define os_printf diag_printf

// CONFIG_ESA and CONFIG_BOOL are defined in redboot/include/flash_config.h
#ifndef CONFIG_ESA
#define CONFIG_ESA 6      // ethernet address length ...
#endif

#ifndef CONFIG_BOOL
#define CONFIG_BOOL 1
#endif

ETH_DRV_SC(fec_eth0_sc,
           &fec_eth0_info,     // Driver specific data
           "eth0",             // Name for this interface
           fec_eth_start,
           fec_eth_stop,
           fec_eth_control,
           fec_eth_can_send,
           fec_eth_send,
           fec_eth_recv,
           fec_eth_deliver,
           fec_eth_int,
           fec_eth_int_vector);

NETDEVTAB_ENTRY(fec_netdev, 
                "fec_eth", 
                fec_eth_init, 
                &fec_eth0_sc);

#ifdef CYGPKG_NET
static cyg_interrupt fec_eth_interrupt;
static cyg_handle_t  fec_eth_interrupt_handle;
#endif
static void          fec_eth_int(struct eth_drv_sc *data);

#define FEC_ETH_INT CYGNUM_HAL_INTERRUPT_FCC2

// This ISR is called when the ethernet interrupt occurs
#ifdef CYGPKG_NET
static int
fec_eth_isr(cyg_vector_t vector, cyg_addrword_t data, HAL_SavedRegisters *regs)
{
  cyg_drv_interrupt_mask(FEC_ETH_INT);
  return (CYG_ISR_HANDLED|CYG_ISR_CALL_DSR);  // Run the DSR
}
#endif

// Deliver function (ex-DSR) handles the ethernet [logical] processing
static void
fec_eth_deliver(struct eth_drv_sc * sc)
{
  fec_eth_int(sc);
#ifdef CYGPKG_NET
  //  Clearing the event register acknowledges FCC2 interrupt ...
  //  cyg_drv_interrupt_acknowledge(FEC_ETH_INT);
  cyg_drv_interrupt_unmask(FEC_ETH_INT);
#endif

}


// Initialize the interface - performed at system startup
// This function must set up the interface, including arranging to
// handle interrupts, etc, so that it may be "started" cheaply later.
static bool 
fec_eth_init(struct cyg_netdevtab_entry *tab)
{
    struct eth_drv_sc *sc = (struct eth_drv_sc *)tab->device_instance;
    struct fec_eth_info *qi = (struct fec_eth_info *)sc->driver_private;

    volatile t_PQ2IMM    *IMM = (volatile t_PQ2IMM *) QUICC2_VADS_IMM_BASE;
    volatile t_Fcc_Pram  *fcc =  (volatile t_Fcc_Pram *) (QUICC2_VADS_IMM_BASE + FEC_PRAM_OFFSET);
    volatile t_EnetFcc_Pram *E_fcc = &(fcc->SpecificProtocol.e);
#if defined(CYGPKG_HAL_POWERPC_VADS) || defined(CYGPKG_HAL_POWERPC_TS6)
    volatile t_BCSR *CSR   = (t_BCSR *) 0x04500000;
#endif

    int i;
    bool esa_ok;
    bool fec_100;
    unsigned char *c_ptr;
    UINT16 link_speed;

    // Link the memory to the driver control memory
    qi->fcc_reg = & (IMM->fcc_regs[FCC2]);

    // just in case :  disable Transmit and Receive 
    qi->fcc_reg->fcc_gfmr &= ~(FEC_GFMR_EN_Rx | FEC_GFMR_EN_Tx);
    
    // Via BCSR, (re)start LXT970
#if defined(CYGPKG_HAL_POWERPC_VADS) || defined(CYGPKG_HAL_POWERPC_TS6)
    EnableResetPHY(CSR);
#endif

    // Try to read the ethernet address of the transciever ...
#ifdef CYGPKG_REDBOOT
    esa_ok = flash_get_config("fec_100", &fec_100, CONFIG_BOOL);
#else
    esa_ok = CYGACC_CALL_IF_FLASH_CFG_OP(CYGNUM_CALL_IF_FLASH_CFG_GET, 
                                         "fec_100", &fec_100, CONFIG_BOOL);
#endif
    
    link_speed = NOTLINKED;
    if(esa_ok && fec_100){
        // Via MII Management pins, tell LXT970 to initialize 
        os_printf("Attempting to acquire 100 Mbps half_duplex link ...");
        InitEthernetPHY((VUINT32 *) &(IMM->io_regs[PORT_C].pdir),
                        (VUINT32 *) &(IMM->io_regs[PORT_C].pdat),
                        HUNDRED_HD);

        link_speed = LinkTestPHY();
        os_printf("\n");
        if(link_speed == NOTLINKED){
            os_printf("Failed to get 100 Mbps half_duplex link.\n");
        }
    }
    if(link_speed == NOTLINKED){
        os_printf("Attempting to acquire 10 Mbps half_duplex link ...");
        InitEthernetPHY((VUINT32 *) &(IMM->io_regs[PORT_C].pdir),
                        (VUINT32 *) &(IMM->io_regs[PORT_C].pdat),
                        TEN_HD);
        link_speed = LinkTestPHY();
        os_printf("\n");
        if(link_speed == NOTLINKED){
            link_speed = LinkTestPHY();
            os_printf("Failed to get 10 Mbps half_duplex link.\n");
        }
            
    }
    switch ( link_speed ) {
      
    case HUNDRED_FD: 
      os_printf("100 MB full-duplex ethernet link \n"); 
      break;
    case HUNDRED_HD: 
      os_printf("100 MB half-duplex ethernet link \n"); 
      break;
    case TEN_FD: 
      os_printf("10 MB full-duplex ethernet link \n"); 
      break;
    case TEN_HD: 
      os_printf("10 MB half-duplex ethernet link \n"); 
      break;
    default:     
      os_printf("NO ethernet link \n");
    }

    // Connect PORTC pins: (C19) to clk13, (C18) to clk 14
    IMM->io_regs[PORT_C].ppar |= 0x00003000;
    IMM->io_regs[PORT_C].podr &= ~(0x00003000);
    IMM->io_regs[PORT_C].psor &= ~(0x00003000);
    IMM->io_regs[PORT_C].pdir &= ~(0x00003000);

    // Connect clk13 to RxClk and clk14 to TxClk on FCC2
    IMM->cpm_mux_cmxfcr &= 0x7f007f00; // clear fcc2 clocks
    IMM->cpm_mux_cmxfcr |= 0x00250000; // set fcc2 clocks  (see 15-14)
    IMM->cpm_mux_cmxuar  = 0x0000;     // Utopia address reg, just clear

    // Initialize parallel port registers to connect FCC2 to MII
    IMM->io_regs[PORT_B].podr &= 0xffffc000; // clear bits 18-31 
    IMM->io_regs[PORT_B].psor &= 0xffffc000;
    IMM->io_regs[PORT_B].pdir &= 0xffffc000;

    IMM->io_regs[PORT_B].psor |= 0x00000004;
    IMM->io_regs[PORT_B].pdir |= 0x000003c5;
    IMM->io_regs[PORT_B].ppar |= 0x00003fff; 

    // Initialize Receive Buffer Descriptors
    qi->rbase = fec_eth_rxring;
    qi->rxbd  = fec_eth_rxring;
    qi->rnext = fec_eth_rxring;
    c_ptr = fec_eth_rxbufs;

    for(i=0; i<CYGNUM_DEVS_ETH_POWERPC_QUICC2_RxNUM; i++) {
      
      fec_eth_rxring[i].ctrl   = (FEC_BD_Rx_Empty | FEC_BD_Rx_Int);
      fec_eth_rxring[i].length = 0;                   // reset 
      c_ptr = (unsigned char *) ALIGN_TO_CACHE_LINES(c_ptr);
      fec_eth_rxring[i].buffer = (volatile unsigned char *)c_ptr;
      c_ptr += CYGNUM_DEVS_ETH_POWERPC_QUICC2_BUFSIZE;
    }
    
    fec_eth_rxring[CYGNUM_DEVS_ETH_POWERPC_QUICC2_RxNUM-1].ctrl |= FEC_BD_Rx_Wrap;

    // Initialize Transmit Buffer Descriptors
    qi->tbase = fec_eth_txring;
    qi->txbd  = fec_eth_txring;
    qi->tnext = fec_eth_txring;
    c_ptr = fec_eth_txbufs;

    for(i=0; i<CYGNUM_DEVS_ETH_POWERPC_QUICC2_TxNUM; i++) {
      
      fec_eth_txring[i].ctrl   = (FEC_BD_Tx_Pad | FEC_BD_Tx_Int);  
      fec_eth_txring[i].length = 0;   // reset : Write before send
      c_ptr = (unsigned char *) ALIGN_TO_CACHE_LINES(c_ptr);
      fec_eth_txring[i].buffer = (volatile unsigned char  *)c_ptr;
      c_ptr += CYGNUM_DEVS_ETH_POWERPC_QUICC2_BUFSIZE;
    }

    fec_eth_txring[CYGNUM_DEVS_ETH_POWERPC_QUICC2_TxNUM-1].ctrl |= FEC_BD_Tx_Wrap;
    
    // Common FCC Parameter RAM initialization
    fcc->riptr = FEC_PRAM_RIPTR;   // in dual port RAM (see 28-11)
    fcc->tiptr = FEC_PRAM_TIPTR;   // in dual port RAM (see 28-11)
    fcc->mrblr = FEC_PRAM_MRBLR;   // ?? FROM 8101 code ...
    fcc->rstate &= FEC_FCR_INIT;
    fcc->rstate |= FEC_FCR_MOT_BO;
    fcc->rbase = (long) fec_eth_rxring;
    fcc->tstate &= FEC_FCR_INIT;
    fcc->tstate |= FEC_FCR_MOT_BO;
    fcc->tbase = (long) fec_eth_txring;

    // Ethernet Specific FCC Parameter RAM Initialization     
    E_fcc->c_mask   = FEC_PRAM_C_MASK; // (see 30-9)
    E_fcc->c_pres   = FEC_PRAM_C_PRES;
    E_fcc->crcec    = 0;
    E_fcc->alec     = 0;
    E_fcc->disfc    = 0;
    E_fcc->ret_lim  = FEC_PRAM_RETLIM;
    E_fcc->p_per    = FEC_PRAM_PER_LO;
    E_fcc->gaddr_h  = 0;
    E_fcc->gaddr_l  = 0;
    E_fcc->tfcstat  = 0;
    E_fcc->mflr     = FEC_MAX_FLR;

    // Try to read the ethernet address of the transciever ...
#ifdef CYGPKG_REDBOOT
    esa_ok = flash_get_config("fec_esa", enaddr, CONFIG_ESA);
#else
    esa_ok = CYGACC_CALL_IF_FLASH_CFG_OP(CYGNUM_CALL_IF_FLASH_CFG_GET, 
                                         "fec_esa", enaddr, CONFIG_ESA);
#endif
    if (!esa_ok) {
      // If can't use the default ...
      os_printf("FEC_ETH - Warning! ESA unknown\n");
      memcpy(enaddr, _default_enaddr, sizeof(enaddr));
    }

    E_fcc->paddr1_h = ((short)enaddr[5] << 8) | enaddr[4]; // enaddr[2]; 
    E_fcc->paddr1_m = ((short)enaddr[3] << 8) | enaddr[2]; // enaddr[1];
    E_fcc->paddr1_l = ((short)enaddr[1] << 8) | enaddr[0]; // enaddr[0];

    E_fcc->iaddr_h  = 0;