amd_lance.h

来自「eCos操作系统源码」· C头文件 代码 · 共 533 行 · 第 1/2 页

#ifndef CYGONCE_DEVS_ETH_AMD_LANCE_H
#define CYGONCE_DEVS_ETH_AMD_LANCE_H
//==========================================================================
//
//      amd_lance.h
//
//      AMD Lance Ethernet chip
//
//==========================================================================
//####ECOSGPLCOPYRIGHTBEGIN####
// -------------------------------------------
// This file is part of eCos, the Embedded Configurable Operating System.
// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
//
// eCos is free software; you can redistribute it and/or modify it under
// the terms of the GNU General Public License as published by the Free
// Software Foundation; either version 2 or (at your option) any later version.
//
// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or
// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
// for more details.
//
// You should have received a copy of the GNU General Public License along
// with eCos; if not, write to the Free Software Foundation, Inc.,
// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
//
// As a special exception, if other files instantiate templates or use macros
// or inline functions from this file, or you compile this file and link it
// with other works to produce a work based on this file, this file does not
// by itself cause the resulting work to be covered by the GNU General Public
// License. However the source code for this file must still be made available
// in accordance with section (3) of the GNU General Public License.
//
// This exception does not invalidate any other reasons why a work based on
// this file might be covered by the GNU General Public License.
//
// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
// at http://sources.redhat.com/ecos/ecos-license/
// -------------------------------------------
//####ECOSGPLCOPYRIGHTEND####
//####BSDCOPYRIGHTBEGIN####
//
// -------------------------------------------
//
// Portions of this software may have been derived from OpenBSD or other sources,
// and are covered by the appropriate copyright disclaimers included herein.
//
// -------------------------------------------
//
//####BSDCOPYRIGHTEND####
//==========================================================================
//#####DESCRIPTIONBEGIN####
//
// Author(s):    jskov, iz
// Contributors: jskov, hmt, iz
// Date:         2002-07-17
// Purpose:      Hardware description of AMD Lance series.
// Description:  
//
//####DESCRIPTIONEND####
//
//==========================================================================

#include <cyg/hal/hal_io.h>

//------------------------------------------------------------------------
// Get macros from platform header
#define __WANT_CONFIG
#include CYGDAT_DEVS_ETH_AMD_LANCEPCI_INL
#undef  __WANT_CONFIG

//------------------------------------------------------------------------
// Set to perms of:
// 0 disables all debug output
// 1 for process debug output
// 2 for added data IO output: get_reg, put_reg
// 4 for packet allocation/free output
// 8 for only startup status, so we can tell we're installed OK
#define DEBUG 0x0

#if DEBUG & 1
#define DEBUG_FUNCTION() do { os_printf("%s\n", __FUNCTION__); } while (0)
#else
#define DEBUG_FUNCTION() do {} while(0)
#endif

// ------------------------------------------------------------------------
// Macros for keeping track of statistics
#if defined(ETH_DRV_GET_IF_STATS) || defined (ETH_DRV_GET_IF_STATS_UD)
# define KEEP_STATISTICS
#endif

#ifdef KEEP_STATISTICS
# define INCR_STAT( _x_ )        (cpd->stats. _x_ ++)
#else
# define INCR_STAT( _x_ )        CYG_EMPTY_STATEMENT
#endif

//------------------------------------------------------------------------
// Cache translation
#ifndef CYGARC_UNCACHED_ADDRESS
# define CYGARC_UNCACHED_ADDRESS(x) (x)
#endif

//------------------------------------------------------------------------
// Address translation
#ifndef HAL_PCI_CPU_TO_BUS
# error "HAL PCI support must define translation macros"
#endif

// ------------------------------------------------------------------------
// Macros for accessing structure elements

#define _SU8( _base_, _offset_) \
        *((cyg_uint8 *)((CYG_ADDRWORD)_base_+(_offset_)))
#define _SU16( _base_, _offset_) \
        *((cyg_uint16 *)((CYG_ADDRWORD)_base_+(_offset_)))
#define _SU32( _base_, _offset_) \
        *((cyg_uint32 *)((CYG_ADDRWORD)_base_+(_offset_)))

#define _SI8( _base_, _offset_) \
        *((cyg_int8 *)((CYG_ADDRWORD)_base_+(_offset_)))
#define _SI16( _base_, _offset_) \
        *((cyg_int16 *)((CYG_ADDRWORD)_base_+(_offset_)))
#define _SI32( _base_, _offset_) \
        *((cyg_int32 *)((CYG_ADDRWORD)_base_+(_offset_)))

// ------------------------------------------------------------------------
// Macros for accessing controller registers
#ifndef HAL_PCI_IO_READ_UINT8
# define HAL_PCI_IO_READ_UINT8(addr, datum)   HAL_READ_UINT8(addr, datum)
# define HAL_PCI_IO_WRITE_UINT8(addr, datum)  HAL_WRITE_UINT8(addr, datum)
# define HAL_PCI_IO_READ_UINT16(addr, datum)  HAL_READ_UINT16(addr, datum)
# define HAL_PCI_IO_WRITE_UINT16(addr, datum) HAL_WRITE_UINT16(addr, datum)
# define HAL_PCI_IO_READ_UINT32(addr, datum)  HAL_READ_UINT32(addr, datum)
# define HAL_PCI_IO_WRITE_UINT32(addr, datum) HAL_WRITE_UINT32(addr, datum)
#endif

// ------------------------------------------------------------------------
// IO map registers
#define LANCE_IO_EEPROM   0x00
#define LANCE_IO_ID       0x0e
#define LANCE_IO_RDP      0x10
#define LANCE_IO_RAP      0x12
#define LANCE_IO_RESET    0x14
#define LANCE_IO_BDP      0x16

// The ID of the 79C790 is 0x5757 - that may be different in other
// (older) cards.
#define LANCE_IO_ID_KEY   0x5757

// ------------------------------------------------------------------------
// Controller registers come in three sets: CSR, BCR and ANR. Use
// high-bits do differentiate, make the put/get functions do the right
// thing depending the state of these bits.
#define LANCE_RAP_MASK    0x007f
//#define LANCE_CSR_FLAG  0x0000        // implied
#define LANCE_BCR_FLAG    0x0080
#define LANCE_ANR_FLAG    0x0100


// CSR registers
#define LANCE_CSR_CSCR    0
#define LANCE_CSR_IBA0    1
#define LANCE_CSR_IBA1    2
#define LANCE_CSR_IM      3
#define LANCE_CSR_TFC     4
#define LANCE_CSR_ECI     5
#define LANCE_CSR_LAR0    8
#define LANCE_CSR_LAR1    9
#define LANCE_CSR_LAR2    10
#define LANCE_CSR_LAR3    11
#define LANCE_CSR_PAR0    12
#define LANCE_CSR_PAR1    13
#define LANCE_CSR_PAR2    14
#define LANCE_CSR_MODE    15
#define LANCE_CSR_BARRL   24
#define LANCE_CSR_BARRU   25
#define LANCE_CSR_BATRL   30
#define LANCE_CSR_BATRU   31
#define LANCE_CSR_RRC     72
#define LANCE_CSR_TRC     74
#define LANCE_CSR_RRLEN   76
#define LANCE_CSR_TRLEN   78
#define LANCE_CSR_ID_LO   88
#define LANCE_CSR_ID_HI   89


#define LANCE_CSR_CSCR_ERR       0x8000
#define LANCE_CSR_CSCR_RES       0x4000
#define LANCE_CSR_CSCR_CERR      0x2000
#define LANCE_CSR_CSCR_MISS      0x1000
#define LANCE_CSR_CSCR_MERR      0x0800
#define LANCE_CSR_CSCR_RINT      0x0400
#define LANCE_CSR_CSCR_TINT      0x0200
#define LANCE_CSR_CSCR_IDON      0x0100
#define LANCE_CSR_CSCR_INTR      0x0080
#define LANCE_CSR_CSCR_IENA      0x0040
#define LANCE_CSR_CSCR_RXON      0x0020
#define LANCE_CSR_CSCR_TXON      0x0010
#define LANCE_CSR_CSCR_TDMD      0x0008
#define LANCE_CSR_CSCR_STOP      0x0004
#define LANCE_CSR_CSCR_STRT      0x0002
#define LANCE_CSR_CSCR_INIT      0x0001

#define LANCE_CSR_CSCR_EV_MASK   0x007f

#define LANCE_CSR_IM_MISSM       0x1000
#define LANCE_CSR_IM_MERRM       0x0800
#define LANCE_CSR_IM_RINTM       0x0400
#define LANCE_CSR_IM_TINTM       0x0200
#define LANCE_CSR_IM_IDONM       0x0100
#define LANCE_CSR_IM_DXSUFLO     0x0040
#define LANCE_CSR_IM_LAPPEN      0x0020
#define LANCE_CSR_IM_DXMT2PD     0x0010
#define LANCE_CSR_IM_EMBA        0x0008
#define LANCE_CSR_IM_BSWP        0x0004

#define LANCE_CSR_TFC_TXDPOLL    0x1000
#define LANCE_CSR_TFC_APAD_XMT   0x0800
#define LANCE_CSR_TFC_ASTRP_RCV  0x0400
#define LANCE_CSR_TFC_MFCO       0x0200
#define LANCE_CSR_TFC_MFCOM      0x0100
#define LANCE_CSR_TFC_UINTCMD    0x0080
#define LANCE_CSR_TFC_UINT       0x0040
#define LANCE_CSR_TFC_RCVCCO     0x0020
#define LANCE_CSR_TFC_RCVCCOM    0x0010
#define LANCE_CSR_TFC_TXSTRT     0x0008
#define LANCE_CSR_TFC_TXSTRTM    0x0004

#define LANCE_CSR_ECI_TOKINTD      0x8000
#define LANCE_CSR_ECI_LTINTEN      0x4000
#define LANCE_CSR_ECI_SINT         0x0800
#define LANCE_CSR_ECI_SINTE        0x0400
#define LANCE_CSR_ECI_EXDINT       0x0080
#define LANCE_CSR_ECI_EXDINTE      0x0040
#define LANCE_CSR_ECI_MPPLBA       0x0020
#define LANCE_CSR_ECI_MPINT        0x0010
#define LANCE_CSR_ECI_MPINTE       0x0008
#define LANCE_CSR_ECI_MPEN         0x0004
#define LANCE_CSR_ECI_MPMODE       0x0002
#define LANCE_CSR_ECI_SPND         0x0001

#define LANCE_CSR_MODE_PROM        0x8000
#define LANCE_CSR_MODE_DRCVBC      0x4000
#define LANCE_CSR_MODE_DRCVPA      0x2000
#define LANCE_CSR_MODE_PORTSEL     0x0180
#define LANCE_CSR_MODE_INTL        0x0040
#define LANCE_CSR_MODE_DRTY        0x0020
#define LANCE_CSR_MODE_FCOLL       0x0010
#define LANCE_CSR_MODE_DXMTFCS     0x0008
#define LANCE_CSR_MODE_LOOP        0x0004
#define LANCE_CSR_MODE_DTX         0x0002
#define LANCE_CSR_MODE_DRX         0x0001

// BCR registers
#define LANCE_BCR_SWSTYLE (20 |LANCE_BCR_FLAG)
#define LANCE_BCR_MIIADDR (33 |LANCE_BCR_FLAG)
#define LANCE_BCR_MIIDATA (34 |LANCE_BCR_FLAG)

#define LANCE_BCR_MIIADDR_PHYAD    0x03e0


//----------------------------------------------------------------------------
// Receive buffer Descriptor
#if 1