cpu.h

eCos操作系统源码

    fp_reg        _f3;
    fp_reg        _f4;
    fp_reg        _f5;
    fp_reg        _f6;
    fp_reg        _f7;
    unsigned long _fps;
    unsigned long _cpsr;

    unsigned long _spsvc;  /* saved svc mode sp */

  } ex_regs_t;
#endif
#   define   _sp  _r13
#   define   _lr  _r14

extern void __icache_flush(void *addr, int nbytes);
extern void __dcache_flush(void *addr, int nbytes);

#endif /* __ASSEMBLER__ */


/*
 * Program Status Register Definitions
 */
#if defined(__ASSEMBLER__)
#  define ARM_PSR_NEGATIVE       0x80000000  /* Negative Bit                           */
#  define ARM_PSR_ZERO           0x40000000  /* Zero Bit                               */
#  define ARM_PSR_CARRY          0x20000000  /* Carry Bit                              */
#  define ARM_PSR_OVERFLOW       0x10000000  /* Overflow Bit                           */
#  define ARM_PSR_IRQ            0x00000080  /* IRQ Bit                                */
#  define ARM_PSR_FIQ            0x00000040  /* FIQ Bit                                */
#  define ARM_PSR_THUMB_STATE    0x00000020  /* Thumb/ARM(R) Execution                 */
#  define ARM_PSR_MODE_MASK      0x0000001F  /* ARM(R) Processor Mode Mask             */
#else /* ! defined(__ASSEMBLER__) */
  struct psr_struct {
      unsigned mode      : 5;
      unsigned t_bit     : 1;
      unsigned f_bit     : 1;
      unsigned i_bit     : 1;
      unsigned rsv1      : 20;  /* == 0x00000 */
      unsigned v_bit     : 1;
      unsigned c_bit     : 1;
      unsigned z_bit     : 1;
      unsigned n_bit     : 1;
  };

  union arm_psr {
      unsigned long word;
      struct psr_struct psr;
  };
#endif /* __ASSEMBLER__ */

/*
 * PSR Mode values
 */
#define ARM_PSR_MODE_USER      0x00000010  /* User mode                              */
#define ARM_PSR_MODE_FIQ       0x00000011  /* FIQ mode                               */
#define ARM_PSR_MODE_IRQ       0x00000012  /* IRQ mode                               */
#define ARM_PSR_MODE_SVC       0x00000013  /* SVC mode                               */
#define ARM_PSR_MODE_ABORT     0x00000017  /* ABORT mode                             */
#define ARM_PSR_MODE_UNDEF     0x0000001B  /* UNDEF mode                             */
#define ARM_PSR_MODE_SYSTEM    0x0000001F  /* System Mode                            */
#define ARM_PSR_NUM_MODES      7

/*
 * Core Exception vectors.
 */
#define BSP_CORE_EXC_RESET                     0
#define BSP_CORE_EXC_UNDEFINED_INSTRUCTION     1
#define BSP_CORE_EXC_SOFTWARE_INTERRUPT        2
#define BSP_CORE_EXC_PREFETCH_ABORT            3
#define BSP_CORE_EXC_DATA_ABORT                4
#define BSP_CORE_EXC_ADDRESS_ERROR_26_BIT      5
#define BSP_CORE_EXC_IRQ                       6
#define BSP_CORE_EXC_FIQ                       7
#define BSP_MAX_EXCEPTIONS                     8
#define BSP_CORE_EXC(vec_num)                  (unsigned long*)(vec_num << 2)

#define BREAKPOINT_INSN                        0xE7FFDEFE   /* Illegal inst opcode */
#define SYSCALL_SWI                            0x00180001

#if defined(__ASSEMBLER__)
  .macro BREAKPOINT
         .word BREAKPOINT_INSN
  .endm
  .macro SYSCALL
         swi  IMM(SYSCALL_SWI)
  .endm
  .macro __CLI
         stmfd  sp!, {r0}
         mrs    r0, cpsr
         bic    r0, r0, IMM(ARM_PSR_IRQ | ARM_PSR_FIQ)
         msr    cpsr, r0
         ldmfd  sp!, {r0}
  .endm
  .macro __STI
         stmfd  sp!, {r0}
         mrs    r0, cpsr
         orr    r0, r0, IMM(ARM_PSR_IRQ | ARM_PSR_FIQ)
         msr    cpsr, r0
         ldmfd  sp!, {r0}
  .endm

#  if 0
  /*
   * Use this code to verify a particular processing mode
   */
	mrs	r0, cpsr
        and     r0, r0, IMM(ARM_PSR_MODE_MASK)
        ldr     r1, =ARM_PSR_MODE_IRQ
        cmps    r0, r1
0:      bne     0b
        PORT_TOGGLE_DEBUG
#  endif /* 0 */

#else /* !defined(__ASSEMBLER__) */

#  define BREAKPOINT() asm volatile(" .word 0xE7FFDEFE")
#  define SYSCALL()    asm volatile(" swi   %0" : /* No outputs */ : "i" (SYSCALL_SWI))
#  define __cli()      asm volatile("
         stmfd  sp!, {r0}
         mrs    r0, cpsr
         bic    r0, r0, #0x000000C0
         msr    cpsr, r0
         ldmfd  sp!, {r0}")
#  define __sti()      asm volatile("
         stmfd  sp!, {r0}
         mrs    r0, cpsr
         orr    r0, r0, #0x000000C0
         msr    cpsr, r0
         ldmfd  sp!, {r0}")
#  define __mcr(cp_num, opcode1, Rd, CRn, CRm, opcode2) \
     asm volatile (" mcr " cp_num  ", " \
                           opcode1 ", " \
                           "%0"    ", " \
                           CRn     ", " \
                           CRm     ", " \
                           opcode2 : /* no outputs */ : "r" (Rd))
#  define __mrc(cp_num, opcode1, Rd, CRn, CRm, opcode2) \
     asm volatile (" mrc " cp_num  ", " \
                           opcode1 ", " \
                           "%0"    ", " \
                           CRn     ", " \
                           CRm     ", " \
                           opcode2 : "=r" (Rd) : /* no inputs */)

  static inline unsigned __get_cpsr(void)
  {
      unsigned long retval;
      asm volatile (" mrs  %0, cpsr" : "=r" (retval) : /* no inputs */  );
      return retval;
  }

  static inline void __set_cpsr(unsigned val)
  {
      asm volatile (" msr  cpsr, %0" : /* no outputs */ : "r" (val)  );
  }

  static inline unsigned __get_spsr(void)
  {
      unsigned long retval;
      asm volatile (" mrs  %0, spsr" : "=r" (retval) : /* no inputs */  );
      return retval;
  }

  static inline void __set_spsr(unsigned val)
  {
      asm volatile (" msr  spsr, %0" : /* no outputs */ : "r" (val)  );
  }

  static inline unsigned __get_sp(void)
  {
      unsigned long retval;
      asm volatile (" mov  %0, sp" : "=r" (retval) : /* no inputs */  );
      return retval;
  }

  static inline void __set_sp(unsigned val)
  {
      asm volatile (" mov  sp, %0" : /* no outputs */ : "r" (val)  );
  }

  static inline unsigned __get_fp(void)
  {
      unsigned long retval;
      asm volatile (" mov  %0, fp" : "=r" (retval) : /* no inputs */  );
      return retval;
  }

  static inline void __set_fp(unsigned val)
  {
      asm volatile (" mov  fp, %0" : /* no outputs */ : "r" (val)  );
  }

  static inline unsigned __get_pc(void)
  {
      unsigned long retval;
      asm volatile (" mov  %0, pc" : "=r" (retval) : /* no inputs */  );
      return retval;
  }

  static inline void __set_pc(unsigned val)
  {
      asm volatile (" mov  pc, %0" : /* no outputs */ : "r" (val)  );
  }

  static inline unsigned __get_lr(void)
  {
      unsigned long retval;
      asm volatile (" mov  %0, lr" : "=r" (retval) : /* no inputs */  );
      return retval;
  }

  static inline void __set_lr(unsigned val)
  {
      asm volatile (" mov  lr, %0" : /* no outputs */ : "r" (val)  );
  }

  static inline unsigned __get_r8(void)
  {
      unsigned long retval;
      asm volatile (" mov  %0, r8" : "=r" (retval) : /* no inputs */  );
      return retval;
  }

  static inline void __set_r8(unsigned val)
  {
      asm volatile (" mov  r8, %0" : /* no outputs */ : "r" (val)  );
  }

  static inline unsigned __get_r9(void)
  {
      unsigned long retval;
      asm volatile (" mov  %0, r9" : "=r" (retval) : /* no inputs */  );
      return retval;
  }

  static inline void __set_r9(unsigned val)
  {
      asm volatile (" mov  r9, %0" : /* no outputs */ : "r" (val)  );
  }

  static inline unsigned __get_r10(void)
  {
      unsigned long retval;
      asm volatile (" mov  %0, r10" : "=r" (retval) : /* no inputs */  );
      return retval;
  }

  static inline void __set_r10(unsigned val)
  {
      asm volatile (" mov  r10, %0" : /* no outputs */ : "r" (val)  );
  }

  static inline unsigned __get_r11(void)
  {
      unsigned long retval;
      asm volatile (" mov  %0, r11" : "=r" (retval) : /* no inputs */  );
      return retval;
  }

  static inline void __set_r11(unsigned val)
  {
      asm volatile (" mov  r11, %0" : /* no outputs */ : "r" (val)  );
  }

  static inline unsigned __get_r12(void)
  {
      unsigned long retval;
      asm volatile (" mov  %0, r12" : "=r" (retval) : /* no inputs */  );
      return retval;
  }

  static inline void __set_r12(unsigned val)
  {
      asm volatile (" mov  r12, %0" : /* no outputs */ : "r" (val)  );
  }

#endif /* defined(__ASSEMBLER__) */

#define GDB_BREAKPOINT_VECTOR BSP_CORE_EXC_UNDEFINED_INSTRUCTION
#define GDB_SYSCALL_VECTOR    BSP_CORE_EXC_SOFTWARE_INTERRUPT

#define ARM_INST_SIZE            sizeof(unsigned long)
#define GDB_BREAKPOINT_INST_SIZE ARM_INST_SIZE

#ifdef __CPU_LH77790A__
#  include <bsp/lh77790a.h>
#endif /* __CPU_LH77790A__ */

#if !defined(__ASSEMBLER__)
/*
 * Define the CPU specific data
 */
#ifdef __CPU_LH77790A__
  typedef struct {
      unsigned char lh77790a_port_control_shadow;
  } arm_cpu_data;
#endif /* __CPU_LH77790A__ */
#endif /* !defined(__ASSEMBLER__) */

#ifdef __CPU_SA110__
#include <bsp/sa-110.h>
#endif /* __CPU_SA110__ */

#ifdef __CPU_SA1100__
#include <bsp/sa-1100.h>
#endif /* __CPU_SA110__ */

#ifdef __CPU_710T__
#include <bsp/arm710t.h>
#endif /* __CPU_710T__ */

#ifdef MMU
/*
 * ARM(R) MMU Definitions
 */

#ifndef __ASSEMBLER__
extern void *page1;
#endif /* __ASSEMBLER__ */

/*
 * ARM(R) Cache and MMU Control Registers
 *
 * Accessed through coprocessor instructions.
 */