pci_cfg.h

eCos操作系统源码

#ifndef CYGONCE_PCI_CFG_H
#define CYGONCE_PCI_CFG_H
//=============================================================================
//
//      pci_cfg.h
//
//      PCI configuration definitions
//
//=============================================================================
//####ECOSGPLCOPYRIGHTBEGIN####
// -------------------------------------------
// This file is part of eCos, the Embedded Configurable Operating System.
// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
//
// eCos is free software; you can redistribute it and/or modify it under
// the terms of the GNU General Public License as published by the Free
// Software Foundation; either version 2 or (at your option) any later version.
//
// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or
// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
// for more details.
//
// You should have received a copy of the GNU General Public License along
// with eCos; if not, write to the Free Software Foundation, Inc.,
// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
//
// As a special exception, if other files instantiate templates or use macros
// or inline functions from this file, or you compile this file and link it
// with other works to produce a work based on this file, this file does not
// by itself cause the resulting work to be covered by the GNU General Public
// License. However the source code for this file must still be made available
// in accordance with section (3) of the GNU General Public License.
//
// This exception does not invalidate any other reasons why a work based on
// this file might be covered by the GNU General Public License.
//
// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
// at http://sources.redhat.com/ecos/ecos-license/
// -------------------------------------------
//####ECOSGPLCOPYRIGHTEND####
//=============================================================================
//#####DESCRIPTIONBEGIN####
//
// Author(s):    jskov
// Contributors: jskov
// Date:         1999-08-09
// Purpose:      Provides PCI configuration information
//               (common structure layout & defined vendor/class codes)
// Usage:
//              #include <cyg/io/pci_cfg.h>
//
//####DESCRIPTIONEND####
//
//=============================================================================

//----------------------------------------------------------------------
// PCI Configuration structure offsets
#define CYG_PCI_CFG_VENDOR                      0x00
#define CYG_PCI_CFG_DEVICE                      0x02
#define CYG_PCI_CFG_COMMAND                     0x04
#define CYG_PCI_CFG_STATUS                      0x06
#define CYG_PCI_CFG_CLASS_REV                   0x08
#define CYG_PCI_CFG_CACHE_LINE_SIZE             0x0c
#define CYG_PCI_CFG_LATENCY_TIMER               0x0d
#define CYG_PCI_CFG_HEADER_TYPE                 0x0e
#define CYG_PCI_CFG_BIST                        0x0f
#define CYG_PCI_CFG_BAR_BASE                    0x10
#define CYG_PCI_CFG_BAR_0                       0x10
#define CYG_PCI_CFG_BAR_1                       0x14
#define CYG_PCI_CFG_BAR_2                       0x18
#define CYG_PCI_CFG_BAR_3                       0x1c
#define CYG_PCI_CFG_BAR_4                       0x20
#define CYG_PCI_CFG_BAR_5                       0x24
#define CYG_PCI_CFG_CARDBUS_CIS                 0x28
#define CYG_PCI_CFG_SUB_VENDOR                  0x2c
#define CYG_PCI_CFG_SUB_ID                      0x2e
#define CYG_PCI_CFG_ROM_ADDRESS                 0x30
#define CYG_PCI_CFG_CAP_LIST                    0x34
#define CYG_PCI_CFG_INT_LINE                    0x3c
#define CYG_PCI_CFG_INT_PIN                     0x3d
#define CYG_PCI_CFG_MIN_GNT                     0x3e
#define CYG_PCI_CFG_MAX_LAT                     0x3f

// Bridge configuration offsets
#define CYG_PCI_CFG_PRI_BUS                     0x18
#define CYG_PCI_CFG_SEC_BUS                     0x19
#define CYG_PCI_CFG_SUB_BUS                     0x1a
#define CYG_PCI_CFG_SEC_LATENCY_TIMER           0x1b
#define CYG_PCI_CFG_IO_BASE                     0x1c
#define CYG_PCI_CFG_IO_LIMIT                    0x1d
#define CYG_PCI_CFG_SEC_STATUS                  0x1e
#define CYG_PCI_CFG_MEM_BASE                    0x20
#define CYG_PCI_CFG_MEM_LIMIT                   0x22
#define CYG_PCI_CFG_PREFETCH_BASE               0x24
#define CYG_PCI_CFG_PREFETCH_LIMIT              0x26
#define CYG_PCI_CFG_PREFETCH_BASE_UPPER32       0x28
#define CYG_PCI_CFG_PREFETCH_LIMIT_UPPER32      0x2c
#define CYG_PCI_CFG_IO_BASE_UPPER16             0x30
#define CYG_PCI_CFG_IO_LIMIT_UPPER16            0x32
#define CYG_PCI_CFG_BRIDGE_ROM_ADDRESS          0x38
#define CYG_PCI_CFG_BRIDGE_CONTROL              0x3e


//-----------------------------------------------------------------
// PCI Control bits

// Command
#define CYG_PCI_CFG_COMMAND_IO                    0x0001
#define CYG_PCI_CFG_COMMAND_MEMORY                0x0002
#define CYG_PCI_CFG_COMMAND_MASTER                0x0004
#define CYG_PCI_CFG_COMMAND_SPECIAL               0x0008
#define CYG_PCI_CFG_COMMAND_INVALIDATE            0x0010
#define CYG_PCI_CFG_COMMAND_VGA_SNOOP             0x0020
#define CYG_PCI_CFG_COMMAND_PARITY                0x0040
#define CYG_PCI_CFG_COMMAND_WAIT                  0x0080
#define CYG_PCI_CFG_COMMAND_SERR                  0x0100
#define CYG_PCI_CFG_COMMAND_FAST_BACK             0x0200

// Consider the device active if any of these bits are set.
#define CYG_PCI_CFG_COMMAND_ACTIVE \
    (CYG_PCI_CFG_COMMAND_IO        \
     |CYG_PCI_CFG_COMMAND_MEMORY   \
     |CYG_PCI_CFG_COMMAND_MASTER)

// Header type
#define CYG_PCI_CFG_HEADER_TYPE_MASK              0x7f
#define CYG_PCI_CFG_HEADER_TYPE_MF                0x80

// BAR
#define CYG_PCI_CFG_BAR_SPACE_MASK                0x00000001
#define CYG_PCI_CFG_BAR_SPACE_MEM                 0x00000000
#define CYG_PCI_CFG_BAR_SPACE_IO                  0x00000001

#define CYG_PRI_CFG_BAR_MEM_TYPE_MASK             0x00000006
#define CYG_PRI_CFG_BAR_MEM_TYPE_32               0x00000000
#define CYG_PRI_CFG_BAR_MEM_TYPE_1M               0x00000002
#define CYG_PRI_CFG_BAR_MEM_TYPE_64               0x00000004

#define CYG_PRI_CFG_BAR_MEM_PREFETCH              0x00000008

#define CYG_PRI_CFG_BAR_MEM_MASK                  0xfffffff0
#define CYG_PRI_CFG_BAR_IO_MASK                   0xfffffffc

// Bridge control
#define CYG_PCI_CFG_BRIDGE_CTL_PARITY		0x0001
#define CYG_PCI_CFG_BRIDGE_CTL_SERR		0x0002
#define CYG_PCI_CFG_BRIDGE_CTL_ISA		0x0004
#define CYG_PCI_CFG_BRIDGE_CTL_VGA		0x0008
#define CYG_PCI_CFG_BRIDGE_CTL_MASTER		0x0020
#define CYG_PCI_CFG_BRIDGE_CTL_RESET		0x0040
#define CYG_PCI_CFG_BRIDGE_CTL_FAST_BACK	0x0080

//----------------------------------------------------------------------
// PCI Vendor IDs
/***********************************************************************
   Can be extracted from the PCICODE List at http://www.yourvote.com/pci
   maintained by Jib Boemler. Use the below Perl script and fix any
   bad vendor names by hand.

#!/usr/bin/perl
while(<>) {
    if (/PCI_VENTABLE/) {
	%mvendors = {};
	@vendors = ();
	@codes = ();
	while(<>) {
	    # Collect vendor names and codes.
	    if (m!.*0x([0-9A-F]{4}), \"([^\"]*)\".*!) {
		$c = lc($1);
		$v = uc($2);
		$v =~ tr/-+ \/&.!/______ /;
		$v =~ s/__/_/g;
		$v =~ s/_$//;
		push @vendors, $v;
		push @codes, $c;
		# Count occurences of vendor name.
		$mvendors{$v} += 1;
	    }
	    last if (/;/);
	}
	# Ouput definitions.
	while ($#vendors >= 0) {
	    $v = shift @vendors;
	    $c = shift @codes;

	    $o = "#define CYG_PCI_VENDOR_$v";
	    # If a vendor name occurs more than once, append code
	    # to get unique definitions.
	    if ($mvendors{$v} > 1) {
		$o .= "_0x$c";
	    }
	    print $o . " " x (60-length($o)) . "0x$c\n";
	}
    }
}
***********************************************************************/

//---------------------- AUTO GENERATED START --------------------------
#define CYG_PCI_VENDOR_LOCKHEED_MARTIN                      0x003d
#define CYG_PCI_VENDOR_COMPAQ_0x0e11                        0x0e11
#define CYG_PCI_VENDOR_SYM                                  0x1000
#define CYG_PCI_VENDOR_ATI                                  0x1002
#define CYG_PCI_VENDOR_ULSI                                 0x1003
#define CYG_PCI_VENDOR_VLSI                                 0x1004
#define CYG_PCI_VENDOR_AVANCE_0x1005                        0x1005
#define CYG_PCI_VENDOR_REPLY                                0x1006
#define CYG_PCI_VENDOR_NETFRAME                             0x1007
#define CYG_PCI_VENDOR_EPSON                                0x1008
#define CYG_PCI_VENDOR_PHOENIX                              0x100a
#define CYG_PCI_VENDOR_NSC                                  0x100b
#define CYG_PCI_VENDOR_TSENG_0x100c                         0x100c
#define CYG_PCI_VENDOR_AST                                  0x100d
#define CYG_PCI_VENDOR_WEITEK                               0x100e