📄 cpuinit.h
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#ifndef _cpuinit_H_
#define _cpuinit_H_
void cpu_init(void); //初始化CPU
void iopf_init(void); //初始化IOPF设置寄存器
interrupt void PHANTOM(void); //伪中断程序
//-------------------------------------------------------------------
/*
************************************************************************
*********************** 函数定义 ******************
************************************************************************
*/
//--------------------------------------------------------------------
// 函数名称 : void cpu_init(void)
// 函数说明 : 初始化CPU
// 输入参数 : 无
// 输出参数 : 无
//--------------------------------------------------------------------
void cpu_init()
{
asm(" nop ");
asm(" nop ");
asm(" nop ");
asm(" setc INTM"); //禁止所有中断 ST0.9=INTM
asm(" clrc SXM"); //抑制符号位扩展
asm(" clrc OVM"); //累加器中结果正常溢出
asm(" clrc CNF"); //配置 B0为数据储存器
/*** Configure the System Control and Status registers ***/
* SCSR1=0x00FD; //配置时钟锁相为4倍频CLKOUT=4*10MHZ=40MHZ,MAX CPU freq
/*
bit 15 0: reserved
bit 14 0: CLKOUT = CPUCLK
bit 13-12 00: IDLE1 selected for low-power mode when execute IDLE instruction
bit 11-9 000: PLL x1 mode
bit 8 0: reserved
bit 7 1: 1 = enable ADC module clock
bit 6 1: 1 = enable SCI module clock
bit 5 1: 1 = enable SPI module clock
bit 4 1: 1 = enable CAN module clock
bit 3 1: 1 = enable EVB module clock
bit 2 1: 1 = enable EVA module clock
bit 1 0: reserved
bit 0 1: clear the ILLADR bit
*/
*SCSR2 = (*SCSR2 | 0x000B) & 0x000F;
/*
bit 15-7 0's: reserved
bit 6 0: Input Qualifier Clocks=5 clock
bit 5 0: D'ont write this bit.allows user to disable WD through the WDDIS bit in the WDCR.
bit 4 0: XMIF_HI-Z, 0=normal mode, 1=Hi-Z'd
bit 3 1: disable the boot ROM, enable the FLASH
bit 2 no change MP/MC* bit reflects state of MP/MC* pin
bit 1-0 11: 11 = SARAM mapped to prog and data
*/
/*** Disable the watchdog timer ***/
* WDCR=0x00EF; //禁止看门狗
/*
bits 15-8 0's: reserved
bit 7 1: clear WD flag
bit 6 1: disable the dog
bit 5-3 101: must be written as 101
bit 2-0 111: WDCLK divider = 64 WDCLK= CLKOUT/512
*/
/*** Setup external memory interface for LF2407 ***/
//WSGR = 0x01f8;
WSGR = 0x0000;
/*
bit 15-11 0's: reserved
bit 10-9 00: bus visibility off
bit 8-6 000: 0 wait-state for I/O space
bit 5-3 000: 0 wait-state for data space
bit 2-0 000: 0 wait state for program space
*/
/*** Setup shared I/O pins ***/
*MCRA = 0x0000; /* group A pins */
/*
bit 15 0: 0=IOPB7, 1=TCLKINA
bit 14 0: 0=IOPB6, 1=TDIRA
bit 13 0: 0=IOPB5, 1=T2PWM/T2CMP
bit 12 0: 0=IOPB4, 1=T1PWM/T1CMP
bit 11 0: 0=IOPB3, 1=PWM6
bit 10 0: 0=IOPB2, 1=PWM5
bit 9 0: 0=IOPB1, 1=PWM4
bit 8 0: 0=IOPB0, 1=PWM3
bit 7 0: 0=IOPA7, 1=PWM2
bit 6 0: 0=IOPA6, 1=PWM1
bit 5 0: 0=IOPA5, 1=CAP3
bit 4 0: 0=IOPA4, 1=CAP2/QEP2
bit 3 0: 0=IOPA3, 1=CAP1/QEP1
bit 2 0: 0=IOPA2, 1=XINT1
bit 1 0: 0=IOPA1, 1=SCIRXD
bit 0 0: 0=IOPA0, 1=SCITXD
*/
*MCRB = 0xFE03; /* group B pins */
/*
bit 15 1: 0=reserved, 1=TMS2 (always write as 1)
bit 14 1: 0=reserved, 1=TMS (always write as 1)
bit 13 1: 0=reserved, 1=TD0 (always write as 1)
bit 12 1: 0=reserved, 1=TDI (always write as 1)
bit 11 1: 0=reserved, 1=TCK (always write as 1)
bit 10 1: 0=reserved, 1=EMU1 (always write as 1)
bit 9 1: 0=reserved, 1=EMU0 (always write as 1)
bit 8 0: 0=IOPD0, 1=XINT2/ADCSOC
bit 7 0: 0=IOPC7, 1=CANRX
bit 6 0: 0=IOPC6, 1=CANTX
bit 5 0: 0=IOPC5, 1=SPISTE
bit 4 0: 0=IOPC4, 1=SPICLK
bit 3 0: 0=IOPC3, 1=SPISOMI
bit 2 0: 0=IOPC2, 1=SPISIMO
bit 1 1: 0=IOPC1, 1=BIO*
bit 0 1: 0=IOPC0, 1=W/R*
*/
*MCRC = 0x0001; /* group C pins */
/*
bit 15 0: reserved
bit 14 0: 0=IOPF6, 1=IOPF6
bit 13 0: 0=IOPF5, 1=TCLKINB
bit 12 0: 0=IOPF4, 1=TDIRB
bit 11 0: 0=IOPF3, 1=T4PWM/T4CMP
bit 10 0: 0=IOPF2, 1=T3PWM/T3CMP
bit 9 0: 0=IOPF1, 1=CAP6
bit 8 0: 0=IOPF0, 1=CAP5/QEP4
bit 7 0: 0=IOPE7, 1=CAP4/QEP3
bit 6 0: 0=IOPE6, 1=PWM12
bit 5 0: 0=IOPE5, 1=PWM11
bit 4 0: 0=IOPE4, 1=PWM10
bit 3 0: 0=IOPE3, 1=PWM9
bit 2 0: 0=IOPE2, 1=PWM8
bit 1 0: 0=IOPE1, 1=PWM7
bit 0 1: 0=IOPE0, 1=CLKOUT
*/
/*** Configure IOPA pin as an INPUT ***/
*PADATDIR = *PADATDIR & 0x00FF;
/*** Configure IOPB pin as an INPUT ***/
*PBDATDIR = *PBDATDIR & 0x00FF;
/*** Configure IOPC pin as an INPUT ***/
*PCDATDIR = *PCDATDIR & 0x00FF;
/*** Configure IOPD pin as an INPUT ***/
*PDDATDIR = *PDDATDIR & 0xFEFF;
/*** Configure IOPE pin as an INPUT ***/
*PEDATDIR = *PEDATDIR & 0x00FF;
/*** Configure IOPF pin as an INPUT ***/
*PFDATDIR = *PFDATDIR & 0x7FFF;
/*** Setup timers 1 and 2, and the PWM configuration ***/
*T1CON = 0x0000; /* disable timer 1 */
*T2CON = 0x0000; /* disable timer 2 */
*GPTCONA = 0x0000; /* configure GPTCONA */
*GPTCONB = 0x0000; /* configure GPTCONB */
/*
bit 15 0: reserved
bit 14 0: T2STAT, read-only
bit 13 0: T1STAT, read-only
bit 12-11 00: reserved
bit 10-9 00: T2TOADC, 00 = no timerX event starts ADC
bit 8-7 00: T1TOADC, 00 = no timerX event starts ADC
bit 6 0: TCOMPOE, 0 = Hi-z all timer compare outputs
bit 5-4 00: reserved
bit 3-2 00: TXPIN, 00 = forced low
bit 1-0 00: TXPIN, 00 = forced low
*/
* IMR=0x0000;
/*
bit 15-6 0: reserved
bit 5 0: Level INT6 is masked
bit 4 0: Level INT5 is masked
bit 3 0: Level INT4 is masked
bit 2 0: Level INT3 is masked
bit 1 0: Level INT2 is masked
bit 0 0: Level INT1 is masked
*/
* IFR=0xFFFF; //清除所有中断标志,"写1清0"
}
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