📄 f33x_smbus_eeprom.lst
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254 1 if (temp_char != 0xCC)
255 1 {
256 2 error_flag = 1;
257 2 }
258 1
259 1 // Store the outgoing data buffer at EEPROM address 0x50
260 1 EEPROM_WriteArray(0x50, out_buff, sizeof(out_buff));
261 1
262 1 // Fill the incoming data buffer with data starting at EEPROM address 0x50
263 1 EEPROM_ReadArray(in_buff, 0x50, sizeof(in_buff));
264 1
265 1 // Check that the data that came from the EEPROM is the same as what was
266 1 // sent
267 1 for (i = 0; i < sizeof(in_buff); i++)
268 1 {
269 2 if (in_buff[i] != out_buff[i])
270 2 {
271 3 error_flag = 1;
272 3 }
273 2 }
274 1
275 1 // Indicate communication is good
276 1 if (error_flag == 0)
277 1 {
278 2 // LED = ON indicates that the test passed
279 2 LED = 1;
280 2 }
281 1
282 1 while(1);
283 1
284 1 }
285
286 //-----------------------------------------------------------------------------
287 // Initialization Routines
288 //-----------------------------------------------------------------------------
289
290 //-----------------------------------------------------------------------------
291 // SMBus_Init()
292 //-----------------------------------------------------------------------------
293 //
294 // Return Value : None
295 // Parameters : None
296 //
297 // The SMBus peripheral is configured as follows:
298 // - SMBus enabled
299 // - Slave mode disabled
300 // - Timer1 used as clock source. The maximum SCL frequency will be
301 // approximately 1/3 the Timer1 overflow rate
302 // - Setup and hold time extensions enabled
303 // - Free and SCL low timeout detection enabled
C51 COMPILER V8.09 F33X_SMBUS_EEPROM 12/28/2008 10:19:32 PAGE 6
304 //
305 void SMBus_Init (void)
306 {
307 1 SMB0CF = 0x5D; // Use Timer1 overflows as SMBus clock
308 1 // source;
309 1 // Disable slave mode;
310 1 // Enable setup & hold time extensions;
311 1 // Enable SMBus Free timeout detect;
312 1 // Enable SCL low timeout detect;
313 1
314 1 SMB0CF |= 0x80; // Enable SMBus;
315 1 }
316
317 //-----------------------------------------------------------------------------
318 // Timer1_Init()
319 //-----------------------------------------------------------------------------
320 //
321 // Return Value : None
322 // Parameters : None
323 //
324 // Timer1 is configured as the SMBus clock source as follows:
325 // - Timer1 in 8-bit auto-reload mode
326 // - SYSCLK / 12 as Timer1 clock source
327 // - Timer1 overflow rate => 3 * SMB_FREQUENCY
328 // - The maximum SCL clock rate will be ~1/3 the Timer1 overflow rate
329 // - Timer1 enabled
330 //
331 void Timer1_Init (void)
332 {
333 1 // Make sure the Timer can produce the appropriate frequency in 8-bit mode
334 1 // Supported SMBus Frequencies range from 10kHz to 100kHz. The CKCON register
335 1 // settings may need to change for frequencies outside this range.
336 1 #if ((SYSCLK/SMB_FREQUENCY/3) < 255)
337 1 #define SCALE 1
338 1 CKCON |= 0x08; // Timer1 clock source = SYSCLK
339 1 #elif ((SYSCLK/SMB_FREQUENCY/4/3) < 255)
#define SCALE 4
CKCON |= 0x01;
CKCON &= ~0x0A; // Timer1 clock source = SYSCLK / 4
#endif
344 1
345 1 TMOD = 0x20; // Timer1 in 8-bit auto-reload mode
346 1
347 1 TH1 = -(SYSCLK/SMB_FREQUENCY/12/3); // Timer1 configured to overflow at 1/3
348 1 // the rate defined by SMB_FREQUENCY
349 1
350 1 TL1 = TH1; // Init Timer1
351 1
352 1 TR1 = 1; // Timer1 enabled
353 1 }
354
355 //-----------------------------------------------------------------------------
356 // Timer3_Init()
357 //-----------------------------------------------------------------------------
358 //
359 // Return Value : None
360 // Parameters : None
361 //
362 // Timer3 configured for use by the SMBus low timeout detect feature as
363 // follows:
364 // - Timer3 in 16-bit auto-reload mode
365 // - SYSCLK/12 as Timer3 clock source
C51 COMPILER V8.09 F33X_SMBUS_EEPROM 12/28/2008 10:19:32 PAGE 7
366 // - Timer3 reload registers loaded for a 25ms overflow period
367 // - Timer3 pre-loaded to overflow after 25ms
368 // - Timer3 enabled
369 //
370 void Timer3_Init (void)
371 {
372 1 TMR3CN = 0x00; // Timer3 configured for 16-bit auto-
373 1 // reload, low-byte interrupt disabled
374 1
375 1 CKCON &= ~0x40; // Timer3 uses SYSCLK/12
376 1
377 1 TMR3RL = -(SYSCLK/12/40); // Timer3 configured to overflow after
378 1 TMR3 = TMR3RL; // ~25ms (for SMBus low timeout detect)
379 1
380 1 EIE1 |= 0x80; // Timer3 interrupt enable
381 1 TMR3CN |= 0x04; // Start Timer3
382 1 }
383
384 //-----------------------------------------------------------------------------
385 // PORT_Init
386 //-----------------------------------------------------------------------------
387 //
388 // Return Value : None
389 // Parameters : None
390 //
391 // Configure the Crossbar and GPIO ports.
392 //
393 // P0.0 digital open-drain SMBus SDA
394 // P0.1 digital open-drain SMBus SCL
395 //
396 // P1.3 digital push-pull LED
397 //
398 // all other port pins unused
399 //
400 // Note: If the SMBus is moved, the SCL and SDA sbit declarations must also
401 // be adjusted.
402 //
403 void PORT_Init (void)
404 {
405 1 P0MDOUT = 0x00; // All P0 pins open-drain output
406 1
407 1 P1MDOUT |= 0x08; // Make the LED (P1.3) a push-pull
408 1 // output
409 1
410 1 XBR0 = 0x04; // Enable SMBus pins
411 1 XBR1 = 0x40; // Enable crossbar and weak pull-ups
412 1
413 1 P0 = 0xFF;
414 1 }
415
416 //-----------------------------------------------------------------------------
417 // SMBus Interrupt Service Routine (ISR)
418 //-----------------------------------------------------------------------------
419 //
420 // SMBus ISR state machine
421 // - Master only implementation - no slave or arbitration states defined
422 // - All incoming data is written starting at the global pointer <pSMB_DATA_IN>
423 // - All outgoing data is read from the global pointer <pSMB_DATA_OUT>
424 //
425 void SMBus_ISR (void) interrupt 7
426 {
427 1 bit FAIL = 0; // Used by the ISR to flag failed
C51 COMPILER V8.09 F33X_SMBUS_EEPROM 12/28/2008 10:19:32 PAGE 8
428 1 // transfers
429 1
430 1 static char i; // Used by the ISR to count the
431 1 // number of data bytes sent or
432 1 // received
433 1
434 1 static bit SEND_START = 0; // Send a start
435 1
436 1 switch (SMB0CN & 0xF0) // Status vector
437 1 {
438 2 // Master Transmitter/Receiver: START condition transmitted.
439 2 case SMB_MTSTA:
440 2 SMB0DAT = TARGET; // Load address of the target slave
441 2 SMB0DAT &= 0xFE; // Clear the LSB of the address for the
442 2 // R/W bit
443 2 SMB0DAT |= SMB_RW; // Load R/W bit
444 2 STA = 0; // Manually clear START bit
445 2 i = 0; // Reset data byte counter
446 2 break;
447 2
448 2 // Master Transmitter: Data byte (or Slave Address) transmitted
449 2 case SMB_MTDB:
450 2 if (ACK) // Slave Address or Data Byte
451 2 { // Acknowledged?
452 3 if (SEND_START)
453 3 {
454 4 STA = 1;
455 4 SEND_START = 0;
456 4 break;
457 4 }
458 3 if(SMB_SENDWORDADDR) // Are we sending the word address?
459 3 {
460 4 SMB_SENDWORDADDR = 0; // Clear flag
461 4 SMB0DAT = WORD_ADDR; // Send word address
462 4
463 4 if (SMB_RANDOMREAD)
464 4 {
465 5 SEND_START = 1; // Send a START after the next ACK cycle
466 5 SMB_RW = READ;
467 5 }
468 4
469 4 break;
470 4 }
471 3
472 3 if (SMB_RW==WRITE) // Is this transfer a WRITE?
473 3 {
474 4
475 4 if (i < SMB_DATA_LEN) // Is there data to send?
476 4 {
477 5 // send data byte
478 5 SMB0DAT = *pSMB_DATA_OUT;
479 5
480 5 // increment data out pointer
481 5 pSMB_DATA_OUT++;
482 5
483 5 // increment number of bytes sent
484 5 i++;
485 5 }
486 4 else
487 4 {
488 5 STO = 1; // Set STO to terminte transfer
489 5 SMB_BUSY = 0; // Clear software busy flag
C51 COMPILER V8.09 F33X_SMBUS_EEPROM 12/28/2008 10:19:32 PAGE 9
490 5 }
491 4 }
492 3 else {} // If this transfer is a READ,
493 3 // then take no action. Slave
494 3 // address was transmitted. A
495 3 // separate 'case' is defined
496 3 // for data byte recieved.
497 3 }
498 2 else // If slave NACK,
499 2 {
500 3 if(SMB_ACKPOLL)
501 3 {
502 4 STA = 1; // Restart transfer
503 4 }
504 3 else
505 3 {
506 4 FAIL = 1; // Indicate failed transfer
507 4 } // and handle at end of ISR
508 3 }
509 2 break;
510 2
511 2 // Master Receiver: byte received
512 2 case SMB_MRDB:
513 2 if ( i < SMB_DATA_LEN ) // Is there any data remaining?
514 2 {
515 3 *pSMB_DATA_IN = SMB0DAT; // Store received byte
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