📄 vsb.mdl
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Model {
Name "vsb"
Version 5.0
SaveDefaultBlockParams on
SampleTimeColors off
LibraryLinkDisplay "none"
WideLines on
ShowLineDimensions on
ShowPortDataTypes off
ShowLoopsOnError on
IgnoreBidirectionalLines off
ShowStorageClass off
ExecutionOrder off
RecordCoverage off
CovPath "/"
CovSaveName "covdata"
CovMetricSettings "dw"
CovNameIncrementing off
CovHtmlReporting on
covSaveCumulativeToWorkspaceVar on
CovSaveSingleToWorkspaceVar on
CovCumulativeVarName "covCumulativeData"
CovCumulativeReport off
DataTypeOverride "UseLocalSettings"
MinMaxOverflowLogging "UseLocalSettings"
MinMaxOverflowArchiveMode "Overwrite"
BlockNameDataTip off
BlockParametersDataTip off
BlockDescriptionStringDataTip off
ToolBar on
StatusBar on
BrowserShowLibraryLinks off
BrowserLookUnderMasks off
Created "Fri Sep 05 00:05:14 2008"
UpdateHistory "UpdateHistoryNever"
ModifiedByFormat "%<Auto>"
LastModifiedBy "zhanghui"
ModifiedDateFormat "%<Auto>"
LastModifiedDate "Fri Sep 05 03:48:26 2008"
ModelVersionFormat "1.%<AutoIncrement:3>"
ConfigurationManager "None"
SimParamPage "Solver"
LinearizationMsg "none"
Profile off
ParamWorkspaceSource "MATLABWorkspace"
AccelSystemTargetFile "accel.tlc"
AccelTemplateMakefile "accel_default_tmf"
AccelMakeCommand "make_rtw"
TryForcingSFcnDF off
ExtModeMexFile "ext_comm"
ExtModeBatchMode off
ExtModeTrigType "manual"
ExtModeTrigMode "normal"
ExtModeTrigPort "1"
ExtModeTrigElement "any"
ExtModeTrigDuration 1000
ExtModeTrigHoldOff 0
ExtModeTrigDelay 0
ExtModeTrigDirection "rising"
ExtModeTrigLevel 0
ExtModeArchiveMode "off"
ExtModeAutoIncOneShot off
ExtModeIncDirWhenArm off
ExtModeAddSuffixToVar off
ExtModeWriteAllDataToWs off
ExtModeArmWhenConnect on
ExtModeSkipDownloadWhenConnect off
ExtModeLogAll on
ExtModeAutoUpdateStatusClock on
BufferReuse on
RTWExpressionDepthLimit 5
SimulationMode "normal"
Solver "ode45"
SolverMode "Auto"
StartTime "0.0"
StopTime "10.0"
MaxOrder 5
MaxStep "auto"
MinStep "auto"
MaxNumMinSteps "-1"
InitialStep "auto"
FixedStep "auto"
RelTol "1e-3"
AbsTol "auto"
OutputOption "RefineOutputTimes"
OutputTimes "[]"
Refine "1"
LoadExternalInput off
ExternalInput "[t, u]"
LoadInitialState off
InitialState "xInitial"
SaveTime on
TimeSaveName "tout"
SaveState off
StateSaveName "xout"
SaveOutput on
OutputSaveName "yout"
SaveFinalState off
FinalStateName "xFinal"
SaveFormat "Array"
Decimation "1"
LimitDataPoints on
MaxDataPoints "1000"
SignalLoggingName "sigsOut"
ConsistencyChecking "none"
ArrayBoundsChecking "none"
AlgebraicLoopMsg "warning"
BlockPriorityViolationMsg "warning"
MinStepSizeMsg "warning"
InheritedTsInSrcMsg "warning"
DiscreteInheritContinuousMsg "warning"
MultiTaskRateTransMsg "error"
SingleTaskRateTransMsg "none"
CheckForMatrixSingularity "none"
IntegerOverflowMsg "warning"
Int32ToFloatConvMsg "warning"
ParameterDowncastMsg "error"
ParameterOverflowMsg "error"
ParameterPrecisionLossMsg "warning"
UnderSpecifiedDataTypeMsg "none"
UnnecessaryDatatypeConvMsg "none"
VectorMatrixConversionMsg "none"
InvalidFcnCallConnMsg "error"
SignalLabelMismatchMsg "none"
UnconnectedInputMsg "warning"
UnconnectedOutputMsg "warning"
UnconnectedLineMsg "warning"
SfunCompatibilityCheckMsg "none"
RTWInlineParameters off
BlockReductionOpt on
BooleanDataType off
ConditionallyExecuteInputs on
ParameterPooling on
OptimizeBlockIOStorage on
ZeroCross on
AssertionControl "UseLocalSettings"
ProdHWDeviceType "Microprocessor"
ProdHWWordLengths "8,16,32,32"
RTWSystemTargetFile "grt.tlc"
RTWTemplateMakefile "grt_default_tmf"
RTWMakeCommand "make_rtw"
RTWGenerateCodeOnly off
RTWRetainRTWFile off
TLCProfiler off
TLCDebug off
TLCCoverage off
TLCAssertion off
BlockDefaults {
Orientation "right"
ForegroundColor "black"
BackgroundColor "white"
DropShadow off
NamePlacement "normal"
FontName "Helvetica"
FontSize 10
FontWeight "normal"
FontAngle "normal"
ShowName on
}
BlockParameterDefaults {
Block {
BlockType Product
Inputs "2"
Multiplication "Element-wise(.*)"
ShowAdditionalParam off
InputSameDT on
OutDataTypeMode "Same as first input"
OutDataType "sfix(16)"
OutScaling "2^0"
LockScale off
RndMeth "Floor"
SaturateOnIntegerOverflow on
}
Block {
BlockType Scope
Floating off
ModelBased off
TickLabels "OneTimeTick"
ZoomMode "on"
Grid "on"
TimeRange "auto"
YMin "-5"
YMax "5"
SaveToWorkspace off
SaveName "ScopeData"
LimitDataPoints on
MaxDataPoints "5000"
Decimation "1"
SampleInput off
SampleTime "0"
}
Block {
BlockType Sin
SineType "Time based"
Amplitude "1"
Bias "0"
Frequency "1"
Phase "0"
Samples "10"
Offset "0"
SampleTime "-1"
VectorParams1D on
}
Block {
BlockType StateSpace
A "1"
B "1"
C "1"
D "1"
X0 "0"
AbsoluteTolerance "auto"
Realization "auto"
}
}
AnnotationDefaults {
HorizontalAlignment "center"
VerticalAlignment "middle"
ForegroundColor "black"
BackgroundColor "white"
DropShadow off
FontName "Helvetica"
FontSize 10
FontWeight "normal"
FontAngle "normal"
}
LineDefaults {
FontName "Helvetica"
FontSize 9
FontWeight "normal"
FontAngle "normal"
}
System {
Name "vsb"
Location [99, 221, 774, 490]
Open on
ModelBrowserVisibility off
ModelBrowserWidth 200
ScreenColor "white"
PaperOrientation "landscape"
PaperPositionMode "auto"
PaperType "A4"
PaperUnits "centimeters"
ZoomFactor "100"
ReportName "simulink-default.rpt"
Block {
BlockType Reference
Name "Analog\nFilter Design"
Ports [1, 1]
Position [475, 102, 540, 158]
SourceBlock "dsparch4/Analog\nFilter Design"
SourceType "Analog Filter Design"
method "Butterworth"
filttype "Lowpass"
N "8"
Wlo "60"
Whi "80"
Rp "2"
Rs "40"
}
Block {
BlockType Reference
Name "Analog\nFilter Design1"
Ports [1, 1]
Position [255, 92, 320, 148]
SourceBlock "dsparch4/Analog\nFilter Design"
SourceType "Analog Filter Design"
method "Butterworth"
filttype "Highpass"
N "8"
Wlo "40"
Whi "80"
Rp "2"
Rs "40"
}
Block {
BlockType Product
Name "Product"
Ports [2, 1]
Position [160, 94, 210, 141]
}
Block {
BlockType Product
Name "Product1"
Ports [2, 1]
Position [385, 111, 430, 144]
}
Block {
BlockType Sin
Name "Sine Wave2"
Position [285, 191, 340, 239]
SineType "Time based"
Amplitude "2"
Frequency "5*pi"
Phase "pi/2"
SampleTime "0.01"
}
Block {
BlockType Sin
Name "c(t)"
Position [50, 143, 95, 187]
SineType "Time based"
Frequency "20*pi"
Phase "pi/2"
SampleTime "0.01"
}
Block {
BlockType Sin
Name "m(t)"
Position [45, 82, 90, 128]
SineType "Time based"
Frequency "5*pi"
SampleTime "0.01"
}
Block {
BlockType Scope
Name "vsb"
Ports [1]
Position [375, 27, 410, 73]
Location [526, 341, 1098, 714]
Open on
NumInputPorts "1"
List {
ListType AxesTitles
axes1 "%<SignalLabel>"
}
List {
ListType SelectedSignals
axes1 ""
}
SaveName "ScopeData1"
DataFormat "StructureWithTime"
}
Block {
BlockType Scope
Name "解调后的vsb"
Ports [1]
Position [600, 105, 640, 155]
Location [455, 371, 1029, 741]
Open on
NumInputPorts "1"
ZoomMode "xonly"
List {
ListType AxesTitles
axes1 "%<SignalLabel>"
}
List {
ListType SelectedSignals
axes1 ""
}
TimeRange "10"
YMin "-0.8"
YMax "1"
DataFormat "StructureWithTime"
}
Line {
SrcBlock "m(t)"
SrcPort 1
DstBlock "Product"
DstPort 1
}
Line {
SrcBlock "c(t)"
SrcPort 1
Points [20, 0; 0, -35]
DstBlock "Product"
DstPort 2
}
Line {
SrcBlock "Product1"
SrcPort 1
DstBlock "Analog\nFilter Design"
DstPort 1
}
Line {
SrcBlock "Sine Wave2"
SrcPort 1
Points [5, 0; 0, -80]
DstBlock "Product1"
DstPort 2
}
Line {
SrcBlock "Analog\nFilter Design"
SrcPort 1
DstBlock "解调后的vsb"
DstPort 1
}
Line {
SrcBlock "Product"
SrcPort 1
DstBlock "Analog\nFilter Design1"
DstPort 1
}
Line {
SrcBlock "Analog\nFilter Design1"
SrcPort 1
Points [25, 0]
Branch {
DstBlock "Product1"
DstPort 1
}
Branch {
Points [0, -70]
DstBlock "vsb"
DstPort 1
}
}
}
}
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