dac.fit.rpt

DDS知识解析

; Optimize Hold Timing                                               ; IO Paths and Minimum TPD Paths ; IO Paths and Minimum TPD Paths ;
; Optimize Multi-Corner Timing                                       ; Off                            ; Off                            ;
; PowerPlay Power Optimization                                       ; Normal compilation             ; Normal compilation             ;
; Optimize Timing                                                    ; Normal compilation             ; Normal compilation             ;
; Optimize Timing for ECOs                                           ; Off                            ; Off                            ;
; Regenerate full fit report during ECO compiles                     ; Off                            ; Off                            ;
; Optimize IOC Register Placement for Timing                         ; On                             ; On                             ;
; Limit to One Fitting Attempt                                       ; Off                            ; Off                            ;
; Final Placement Optimizations                                      ; Automatically                  ; Automatically                  ;
; Fitter Aggressive Routability Optimizations                        ; Automatically                  ; Automatically                  ;
; Fitter Initial Placement Seed                                      ; 1                              ; 1                              ;
; PCI I/O                                                            ; Off                            ; Off                            ;
; Weak Pull-Up Resistor                                              ; Off                            ; Off                            ;
; Enable Bus-Hold Circuitry                                          ; Off                            ; Off                            ;
; Auto Global Memory Control Signals                                 ; Off                            ; Off                            ;
; Auto Packed Registers                                              ; Auto                           ; Auto                           ;
; Auto Delay Chains                                                  ; On                             ; On                             ;
; Auto Merge PLLs                                                    ; On                             ; On                             ;
; Ignore PLL Mode When Merging PLLs                                  ; Off                            ; Off                            ;
; Perform Physical Synthesis for Combinational Logic for Fitting     ; Off                            ; Off                            ;
; Perform Physical Synthesis for Combinational Logic for Performance ; Off                            ; Off                            ;
; Perform Register Duplication for Performance                       ; Off                            ; Off                            ;
; Perform Logic to Memory Mapping for Fitting                        ; Off                            ; Off                            ;
; Perform Register Retiming for Performance                          ; Off                            ; Off                            ;
; Perform Asynchronous Signal Pipelining                             ; Off                            ; Off                            ;
; Physical Synthesis Effort Level                                    ; Normal                         ; Normal                         ;
; Auto Global Clock                                                  ; On                             ; On                             ;
; Auto Global Register Control Signals                               ; On                             ; On                             ;
; Stop After Congestion Map Generation                               ; Off                            ; Off                            ;
; Save Intermediate Fitting Results                                  ; Off                            ; Off                            ;
; Maximum number of global clocks allowed                            ; -1                             ; -1                             ;
+--------------------------------------------------------------------+--------------------------------+--------------------------------+


+-----------------------------------------------+
; Incremental Compilation Preservation Summary  ;
+-------------------------+---------------------+
; Type                    ; Value               ;
+-------------------------+---------------------+
; Placement               ;                     ;
;     -- Requested        ; 94 / 970 ( 9.69 % ) ;
;     -- Achieved         ; 88 / 970 ( 9.07 % ) ;
;                         ;                     ;
; Routing (by Connection) ;                     ;
;     -- Requested        ; 55 / 721 ( 7.63 % ) ;
;     -- Achieved         ; 50 / 721 ( 6.93 % ) ;
+-------------------------+---------------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Incremental Compilation Partition Settings                                                                                                                         ;
+----------------------+----------------+-------------------+-------------------------+------------------------+------------------------------+----------------------+
; Partition Name       ; Partition Type ; Netlist Type Used ; Preservation Level Used ; Netlist Type Requested ; Preservation Level Requested ; Contents             ;
+----------------------+----------------+-------------------+-------------------------+------------------------+------------------------------+----------------------+
; Top                  ; User-created   ; Post-Fit          ; Placement and Routing   ; Post-Fit               ; Placement and Routing        ;                      ;
; sld_hub:sld_hub_inst ; Auto-generated ; Source File       ; N/A                     ; Source File            ; N/A                          ; sld_hub:sld_hub_inst ;
; sld_signaltap:dds    ; Auto-generated ; Source File       ; N/A                     ; Source File            ; N/A                          ; sld_signaltap:dds    ;
+----------------------+----------------+-------------------+-------------------------+------------------------+------------------------------+----------------------+


+--------------------------------------------------------------------------------------------------+
; Incremental Compilation Placement Preservation                                                   ;
+----------------------+---------+-------------------+-------------------------+-------------------+
; Partition Name       ; # Nodes ; # Preserved Nodes ; Preservation Level Used ; Netlist Type Used ;
+----------------------+---------+-------------------+-------------------------+-------------------+
; Top                  ; 94      ; 88                ; Placement and Routing   ; Post-Fit          ;
; sld_hub:sld_hub_inst ; 176     ; 0                 ; N/A                     ; Source File       ;
; sld_signaltap:dds    ; 700     ; 0                 ; N/A                     ; Source File       ;
+----------------------+---------+-------------------+-------------------------+-------------------+


+---------------------------------------------------------------------------------------+
; Incremental Compilation Routing Preservation                                          ;
+----------------------+----------------------+---------------+-------------------------+
; Partition 1          ; Partition 2          ; # Connections ; # Preserved Connections ;
+----------------------+----------------------+---------------+-------------------------+
; Top                  ; Top                  ; 204           ; 202                     ;
; sld_hub:sld_hub_inst ; Top                  ; 31            ; 0                       ;
; Top                  ; sld_hub:sld_hub_inst ; 31            ; 0                       ;
; sld_hub:sld_hub_inst ; sld_hub:sld_hub_inst ; 454           ; 0                       ;
; sld_signaltap:dds    ; Top                  ; 113           ; 0                       ;
; Top                  ; sld_signaltap:dds    ; 113           ; 0                       ;
; sld_signaltap:dds    ; sld_hub:sld_hub_inst ; 104           ; 0                       ;
; sld_hub:sld_hub_inst ; sld_signaltap:dds    ; 104           ; 0                       ;
; sld_signaltap:dds    ; sld_signaltap:dds    ; 2250          ; 0                       ;
+----------------------+----------------------+---------------+-------------------------+
Note: The table contains rows with duplicate information to facilitate sorting by Partition.


+------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fitter Incremental Compilation Conflicts                                                                                                             ;
+----------------+-----------------------+---------------+----------------+----------------+-----------------------+---------------+-------------------+
; Ignored Target ; Ignored Setting       ; Ignored Value ; Ignored Type   ; Honored Target ; Honored Setting       ; Honored Value ; Honored Type      ;
+----------------+-----------------------+---------------+----------------+----------------+-----------------------+---------------+-------------------+
; da_data[10]    ; Location              ; PIN 144       ; QSF Assignment ; da_data[10]    ; Location              ; PIN 188       ; Post-Fit Property ;
; da_data[9]     ; Location              ; PIN 142       ; QSF Assignment ; da_data[9]     ; Location              ; PIN 192       ; Post-Fit Property ;
; da_data[8]     ; Location              ; PIN 139       ; QSF Assignment ; da_data[8]     ; Location              ; PIN 185       ; Post-Fit Property ;
; da_data[7]     ; Location              ; PIN 137       ; QSF Assignment ; da_data[7]     ; Location              ; PIN 8         ; Post-Fit Property ;
; da_data[6]     ; Location              ; PIN 134       ; QSF Assignment ; da_data[6]     ; Location              ; PIN 197       ; Post-Fit Property ;
; da_data[5]     ; Location              ; PIN 128       ; QSF Assignment ; da_data[5]     ; Location              ; PIN 191       ; Post-Fit Property ;
; da_data[4]     ; Location              ; PIN 118       ; QSF Assignment ; da_data[4]     ; Location              ; PIN 193       ; Post-Fit Property ;
; da_data[3]     ; Location              ; PIN 117       ; QSF Assignment ; da_data[3]     ; Location              ; PIN 189       ; Post-Fit Property ;
; da_data[2]     ; Location              ; PIN 116       ; QSF Assignment ; da_data[2]     ; Location              ; PIN 11        ; Post-Fit Property ;
; da_data[1]     ; Location              ; PIN 114       ; QSF Assignment ; da_data[1]     ; Location              ; PIN 198       ; Post-Fit Property ;
; da_data[0]     ; Location              ; PIN 113       ; QSF Assignment ; da_data[0]     ; Location              ; PIN 187       ; Post-Fit Property ;
; ~ASDO~         ; Weak Pull-Up Resistor ; OFF           ; QSF Assignment ; ~ASDO~         ; Weak Pull-Up Resistor ; ON            ; Post-Fit Property ;
; ~nCSO~         ; Weak Pull-Up Resistor ; OFF           ; QSF Assignment ; ~nCSO~         ; Weak Pull-Up Resistor ; ON            ; Post-Fit Property ;