📄 dac.fit.rpt
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Fitter report for DAC
Sat Aug 08 18:18:21 2009
Quartus II Version 8.1 Build 163 10/28/2008 SJ Full Version
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; Table of Contents ;
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1. Legal Notice
2. Fitter Summary
3. Fitter Settings
4. Incremental Compilation Preservation Summary
5. Incremental Compilation Partition Settings
6. Incremental Compilation Placement Preservation
7. Incremental Compilation Routing Preservation
8. Fitter Incremental Compilation Conflicts
9. Pin-Out File
10. Fitter Resource Usage Summary
11. Fitter Partition Statistics
12. Input Pins
13. Output Pins
14. I/O Bank Usage
15. All Package Pins
16. Output Pin Default Load For Reported TCO
17. Fitter Resource Utilization by Entity
18. Delay Chain Summary
19. Pad To Core Delay Chain Fanout
20. Control Signals
21. Global & Other Fast Signals
22. Non-Global High Fan-Out Signals
23. Fitter RAM Summary
24. Interconnect Usage Summary
25. LAB Logic Elements
26. LAB-wide Signals
27. LAB Signals Sourced
28. LAB Signals Sourced Out
29. LAB Distinct Inputs
30. Fitter Device Options
31. Operating Settings and Conditions
32. Estimated Delay Added for Hold Timing
33. Advanced Data - General
34. Advanced Data - Placement Preparation
35. Advanced Data - Placement
36. Advanced Data - Routing
37. Fitter Messages
38. Fitter Suppressed Messages
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; Legal Notice ;
----------------
Copyright (C) 1991-2008 Altera Corporation
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, Altera MegaCore Function License
Agreement, or other applicable license agreement, including,
without limitation, that your use is for the sole purpose of
programming logic devices manufactured by Altera and sold by
Altera or its authorized distributors. Please refer to the
applicable agreement for further details.
+-------------------------------------------------------------------------------+
; Fitter Summary ;
+------------------------------------+------------------------------------------+
; Fitter Status ; Successful - Sat Aug 08 18:18:21 2009 ;
; Quartus II Version ; 8.1 Build 163 10/28/2008 SJ Full Version ;
; Revision Name ; DAC ;
; Top-level Entity Name ; DAC ;
; Family ; Cyclone II ;
; Device ; EP2C8Q208C8 ;
; Timing Models ; Final ;
; Total logic elements ; 646 / 8,256 ( 8 % ) ;
; Total combinational functions ; 418 / 8,256 ( 5 % ) ;
; Dedicated logic registers ; 515 / 8,256 ( 6 % ) ;
; Total registers ; 515 ;
; Total pins ; 18 / 138 ( 13 % ) ;
; Total virtual pins ; 0 ;
; Total memory bits ; 24,576 / 165,888 ( 15 % ) ;
; Embedded Multiplier 9-bit elements ; 0 / 36 ( 0 % ) ;
; Total PLLs ; 0 / 2 ( 0 % ) ;
+------------------------------------+------------------------------------------+
+--------------------------------------------------------------------------------------------------------------------------------------+
; Fitter Settings ;
+--------------------------------------------------------------------+--------------------------------+--------------------------------+
; Option ; Setting ; Default Value ;
+--------------------------------------------------------------------+--------------------------------+--------------------------------+
; Device ; EP2C8Q208C8 ; ;
; Minimum Core Junction Temperature ; 0 ; ;
; Maximum Core Junction Temperature ; 85 ; ;
; Fit Attempts to Skip ; 0 ; 0.0 ;
; Device I/O Standard ; 3.3-V LVTTL ; ;
; Fitter Effort ; Standard Fit ; Auto Fit ;
; Use smart compilation ; Off ; Off ;
; Use TimeQuest Timing Analyzer ; Off ; Off ;
; Router Timing Optimization Level ; Normal ; Normal ;
; Placement Effort Multiplier ; 1.0 ; 1.0 ;
; Router Effort Multiplier ; 1.0 ; 1.0 ;
; Always Enable Input Buffers ; Off ; Off ;
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