dac.sim.rpt

DDS知识解析

; |DAC|COUNTER:inst4|lpm_add_sub:lpm_add_sub_component|addcore:adder1[1]|unreg_res_node[1]                       ; |DAC|COUNTER:inst4|lpm_add_sub:lpm_add_sub_component|addcore:adder1[1]|unreg_res_node[1]                       ; out0             ;
; |DAC|COUNTER:inst4|lpm_add_sub:lpm_add_sub_component|addcore:adder1[1]|_~26                                    ; |DAC|COUNTER:inst4|lpm_add_sub:lpm_add_sub_component|addcore:adder1[1]|_~26                                    ; out0             ;
; |DAC|COUNTER:inst4|lpm_add_sub:lpm_add_sub_component|addcore:adder1[1]|_~27                                    ; |DAC|COUNTER:inst4|lpm_add_sub:lpm_add_sub_component|addcore:adder1[1]|_~27                                    ; out0             ;
; |DAC|COUNTER:inst4|lpm_add_sub:lpm_add_sub_component|addcore:adder1[1]|_~28                                    ; |DAC|COUNTER:inst4|lpm_add_sub:lpm_add_sub_component|addcore:adder1[1]|_~28                                    ; out0             ;
; |DAC|COUNTER:inst4|lpm_add_sub:lpm_add_sub_component|addcore:adder1[1]|_~29                                    ; |DAC|COUNTER:inst4|lpm_add_sub:lpm_add_sub_component|addcore:adder1[1]|_~29                                    ; out0             ;
; |DAC|COUNTER:inst4|lpm_add_sub:lpm_add_sub_component|addcore:adder1[1]|_~30                                    ; |DAC|COUNTER:inst4|lpm_add_sub:lpm_add_sub_component|addcore:adder1[1]|_~30                                    ; out0             ;
; |DAC|COUNTER:inst4|lpm_add_sub:lpm_add_sub_component|addcore:adder1[1]|_~31                                    ; |DAC|COUNTER:inst4|lpm_add_sub:lpm_add_sub_component|addcore:adder1[1]|_~31                                    ; out0             ;
; |DAC|COUNTER:inst4|lpm_add_sub:lpm_add_sub_component|addcore:adder1[1]|_~32                                    ; |DAC|COUNTER:inst4|lpm_add_sub:lpm_add_sub_component|addcore:adder1[1]|_~32                                    ; out0             ;
; |DAC|COUNTER:inst4|lpm_add_sub:lpm_add_sub_component|addcore:adder1[1]|_~33                                    ; |DAC|COUNTER:inst4|lpm_add_sub:lpm_add_sub_component|addcore:adder1[1]|_~33                                    ; out0             ;
; |DAC|COUNTER:inst4|lpm_add_sub:lpm_add_sub_component|addcore:adder1[1]|_~34                                    ; |DAC|COUNTER:inst4|lpm_add_sub:lpm_add_sub_component|addcore:adder1[1]|_~34                                    ; out0             ;
; |DAC|COUNTER:inst4|lpm_add_sub:lpm_add_sub_component|addcore:adder1[1]|_~35                                    ; |DAC|COUNTER:inst4|lpm_add_sub:lpm_add_sub_component|addcore:adder1[1]|_~35                                    ; out0             ;
; |DAC|COUNTER:inst4|lpm_add_sub:lpm_add_sub_component|addcore:adder1[1]|_~36                                    ; |DAC|COUNTER:inst4|lpm_add_sub:lpm_add_sub_component|addcore:adder1[1]|_~36                                    ; out0             ;
; |DAC|COUNTER:inst4|lpm_add_sub:lpm_add_sub_component|addcore:adder1[1]|a_csnbuffer:result_node|cs_buffer[11]   ; |DAC|COUNTER:inst4|lpm_add_sub:lpm_add_sub_component|addcore:adder1[1]|a_csnbuffer:result_node|cs_buffer[11]   ; sout             ;
; |DAC|COUNTER:inst4|lpm_add_sub:lpm_add_sub_component|addcore:adder1[1]|a_csnbuffer:result_node|cs_buffer[10]   ; |DAC|COUNTER:inst4|lpm_add_sub:lpm_add_sub_component|addcore:adder1[1]|a_csnbuffer:result_node|cout[10]        ; cout             ;
; |DAC|COUNTER:inst4|lpm_add_sub:lpm_add_sub_component|addcore:adder1[1]|a_csnbuffer:result_node|cs_buffer[10]   ; |DAC|COUNTER:inst4|lpm_add_sub:lpm_add_sub_component|addcore:adder1[1]|a_csnbuffer:result_node|cs_buffer[10]   ; sout             ;
; |DAC|COUNTER:inst4|lpm_add_sub:lpm_add_sub_component|addcore:adder1[1]|a_csnbuffer:result_node|cs_buffer[9]    ; |DAC|COUNTER:inst4|lpm_add_sub:lpm_add_sub_component|addcore:adder1[1]|a_csnbuffer:result_node|cout[9]         ; cout             ;
; |DAC|COUNTER:inst4|lpm_add_sub:lpm_add_sub_component|addcore:adder1[1]|a_csnbuffer:result_node|cs_buffer[9]    ; |DAC|COUNTER:inst4|lpm_add_sub:lpm_add_sub_component|addcore:adder1[1]|a_csnbuffer:result_node|cs_buffer[9]    ; sout             ;
; |DAC|COUNTER:inst4|lpm_add_sub:lpm_add_sub_component|addcore:adder1[1]|a_csnbuffer:result_node|cs_buffer[8]    ; |DAC|COUNTER:inst4|lpm_add_sub:lpm_add_sub_component|addcore:adder1[1]|a_csnbuffer:result_node|cout[8]         ; cout             ;
; |DAC|COUNTER:inst4|lpm_add_sub:lpm_add_sub_component|addcore:adder1[1]|a_csnbuffer:result_node|cs_buffer[8]    ; |DAC|COUNTER:inst4|lpm_add_sub:lpm_add_sub_component|addcore:adder1[1]|a_csnbuffer:result_node|cs_buffer[8]    ; sout             ;
; |DAC|COUNTER:inst4|lpm_add_sub:lpm_add_sub_component|addcore:adder1[1]|a_csnbuffer:result_node|cs_buffer[7]    ; |DAC|COUNTER:inst4|lpm_add_sub:lpm_add_sub_component|addcore:adder1[1]|a_csnbuffer:result_node|cout[7]         ; cout             ;
; |DAC|COUNTER:inst4|lpm_add_sub:lpm_add_sub_component|addcore:adder1[1]|a_csnbuffer:result_node|cs_buffer[7]    ; |DAC|COUNTER:inst4|lpm_add_sub:lpm_add_sub_component|addcore:adder1[1]|a_csnbuffer:result_node|cs_buffer[7]    ; sout             ;
; |DAC|COUNTER:inst4|lpm_add_sub:lpm_add_sub_component|addcore:adder1[1]|a_csnbuffer:result_node|cs_buffer[6]    ; |DAC|COUNTER:inst4|lpm_add_sub:lpm_add_sub_component|addcore:adder1[1]|a_csnbuffer:result_node|cout[6]         ; cout             ;
; |DAC|COUNTER:inst4|lpm_add_sub:lpm_add_sub_component|addcore:adder1[1]|a_csnbuffer:result_node|cs_buffer[6]    ; |DAC|COUNTER:inst4|lpm_add_sub:lpm_add_sub_component|addcore:adder1[1]|a_csnbuffer:result_node|cs_buffer[6]    ; sout             ;
; |DAC|COUNTER:inst4|lpm_add_sub:lpm_add_sub_component|addcore:adder1[1]|a_csnbuffer:result_node|cs_buffer[5]    ; |DAC|COUNTER:inst4|lpm_add_sub:lpm_add_sub_component|addcore:adder1[1]|a_csnbuffer:result_node|cout[5]         ; cout             ;
; |DAC|COUNTER:inst4|lpm_add_sub:lpm_add_sub_component|addcore:adder1[1]|a_csnbuffer:result_node|cs_buffer[5]    ; |DAC|COUNTER:inst4|lpm_add_sub:lpm_add_sub_component|addcore:adder1[1]|a_csnbuffer:result_node|cs_buffer[5]    ; sout             ;
; |DAC|COUNTER:inst4|lpm_add_sub:lpm_add_sub_component|addcore:adder1[1]|a_csnbuffer:result_node|cs_buffer[4]    ; |DAC|COUNTER:inst4|lpm_add_sub:lpm_add_sub_component|addcore:adder1[1]|a_csnbuffer:result_node|cout[4]         ; cout             ;
; |DAC|COUNTER:inst4|lpm_add_sub:lpm_add_sub_component|addcore:adder1[1]|a_csnbuffer:result_node|cs_buffer[4]    ; |DAC|COUNTER:inst4|lpm_add_sub:lpm_add_sub_component|addcore:adder1[1]|a_csnbuffer:result_node|cs_buffer[4]    ; sout             ;
; |DAC|COUNTER:inst4|lpm_add_sub:lpm_add_sub_component|addcore:adder1[1]|a_csnbuffer:result_node|cs_buffer[3]    ; |DAC|COUNTER:inst4|lpm_add_sub:lpm_add_sub_component|addcore:adder1[1]|a_csnbuffer:result_node|cout[3]         ; cout             ;
; |DAC|COUNTER:inst4|lpm_add_sub:lpm_add_sub_component|addcore:adder1[1]|a_csnbuffer:result_node|cs_buffer[3]    ; |DAC|COUNTER:inst4|lpm_add_sub:lpm_add_sub_component|addcore:adder1[1]|a_csnbuffer:result_node|cs_buffer[3]    ; sout             ;
; |DAC|COUNTER:inst4|lpm_add_sub:lpm_add_sub_component|addcore:adder1[1]|a_csnbuffer:result_node|cs_buffer[2]    ; |DAC|COUNTER:inst4|lpm_add_sub:lpm_add_sub_component|addcore:adder1[1]|a_csnbuffer:result_node|cout[2]         ; cout             ;
; |DAC|COUNTER:inst4|lpm_add_sub:lpm_add_sub_component|addcore:adder1[1]|a_csnbuffer:result_node|cs_buffer[2]    ; |DAC|COUNTER:inst4|lpm_add_sub:lpm_add_sub_component|addcore:adder1[1]|a_csnbuffer:result_node|cs_buffer[2]    ; sout             ;
; |DAC|COUNTER:inst4|lpm_add_sub:lpm_add_sub_component|addcore:adder1[1]|a_csnbuffer:result_node|cs_buffer[1]    ; |DAC|COUNTER:inst4|lpm_add_sub:lpm_add_sub_component|addcore:adder1[1]|a_csnbuffer:result_node|cout[1]         ; cout             ;
; |DAC|COUNTER:inst4|lpm_add_sub:lpm_add_sub_component|addcore:adder1[1]|a_csnbuffer:result_node|cs_buffer[1]    ; |DAC|COUNTER:inst4|lpm_add_sub:lpm_add_sub_component|addcore:adder1[1]|a_csnbuffer:result_node|cs_buffer[1]    ; sout             ;
; |DAC|COUNTER:inst4|lpm_add_sub:lpm_add_sub_component|addcore:adder1[1]|a_csnbuffer:result_node|cs_buffer[0]    ; |DAC|COUNTER:inst4|lpm_add_sub:lpm_add_sub_component|addcore:adder1[1]|a_csnbuffer:result_node|cout[0]         ; cout             ;
; |DAC|COUNTER:inst4|lpm_add_sub:lpm_add_sub_component|addcore:adder1[1]|a_csnbuffer:result_node|cs_buffer[0]    ; |DAC|COUNTER:inst4|lpm_add_sub:lpm_add_sub_component|addcore:adder1[1]|a_csnbuffer:result_node|cs_buffer[0]    ; sout             ;
; |DAC|ROM:inst2|altsyncram:altsyncram_component|altsyncram_b331:auto_generated|ram_block1a0                     ; |DAC|ROM:inst2|altsyncram:altsyncram_component|altsyncram_b331:auto_generated|q_a[0]                           ; portadataout0    ;
; |DAC|ROM:inst2|altsyncram:altsyncram_component|altsyncram_b331:auto_generated|ram_block1a1                     ; |DAC|ROM:inst2|altsyncram:altsyncram_component|altsyncram_b331:auto_generated|q_a[1]                           ; portadataout0    ;
; |DAC|ROM:inst2|altsyncram:altsyncram_component|altsyncram_b331:auto_generated|ram_block1a2                     ; |DAC|ROM:inst2|altsyncram:altsyncram_component|altsyncram_b331:auto_generated|q_a[2]                           ; portadataout0    ;
; |DAC|ROM:inst2|altsyncram:altsyncram_component|altsyncram_b331:auto_generated|ram_block1a3                     ; |DAC|ROM:inst2|altsyncram:altsyncram_component|altsyncram_b331:auto_generated|q_a[3]                           ; portadataout0    ;
; |DAC|ROM:inst2|altsyncram:altsyncram_component|altsyncram_b331:auto_generated|ram_block1a4                     ; |DAC|ROM:inst2|altsyncram:altsyncram_component|altsyncram_b331:auto_generated|q_a[4]                           ; portadataout0    ;
; |DAC|ROM:inst2|altsyncram:altsyncram_component|altsyncram_b331:auto_generated|ram_block1a5                     ; |DAC|ROM:inst2|altsyncram:altsyncram_component|altsyncram_b331:auto_generated|q_a[5]                           ; portadataout0    ;
; |DAC|ROM:inst2|altsyncram:altsyncram_component|altsyncram_b331:auto_generated|ram_block1a6                     ; |DAC|ROM:inst2|altsyncram:altsyncram_component|altsyncram_b331:auto_generated|q_a[6]                           ; portadataout0    ;
; |DAC|ROM:inst2|altsyncram:altsyncram_component|altsyncram_b331:auto_generated|ram_block1a7                     ; |DAC|ROM:inst2|altsyncram:altsyncram_component|altsyncram_b331:auto_generated|q_a[7]                           ; portadataout0    ;
; |DAC|ROM:inst2|altsyncram:altsyncram_component|altsyncram_b331:auto_generated|ram_block1a8                     ; |DAC|ROM:inst2|altsyncram:altsyncram_component|altsyncram_b331:auto_generated|q_a[8]                           ; portadataout0    ;
; |DAC|ROM:inst2|altsyncram:altsyncram_component|altsyncram_b331:auto_generated|ram_block1a9                     ; |DAC|ROM:inst2|altsyncram:altsyncram_component|altsyncram_b331:auto_generated|q_a[9]                           ; portadataout0    ;
; |DAC|ROM:inst2|altsyncram:altsyncram_component|altsyncram_b331:auto_generated|ram_block1a10                    ; |DAC|ROM:inst2|altsyncram:altsyncram_component|altsyncram_b331:auto_generated|q_a[10]                          ; portadataout0    ;
; |DAC|ROM:inst2|altsyncram:altsyncram_component|altsyncram_b331:auto_generated|ram_block1a11                    ; |DAC|ROM:inst2|altsyncram:altsyncram_component|altsyncram_b331:auto_generated|q_a[11]                          ; portadataout0    ;
; |DAC|clk_div:inst|clk_reg                                                                                      ; |DAC|clk_div:inst|clk_reg                                                                                      ; regout           ;
+----------------------------------------------------------------------------------------------------------------+----------------------------------------------------------------------------------------------------------------+------------------+


The following table displays output ports that do not toggle to 1 during simulation.
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Missing 1-Value Coverage                                                                                                                                                                           ;
+----------------------------------------------------------------------------------------+----------------------------------------------------------------------------------------+------------------+
; Node Name                                                                              ; Output Port Name                                                                       ; Output Port Type ;
+----------------------------------------------------------------------------------------+----------------------------------------------------------------------------------------+------------------+
; |DAC|clk_div:inst|clk_num[0]                                                           ; |DAC|clk_div:inst|clk_num[0]                                                           ; regout           ;
; |DAC|clk_div:inst|clk_num~0                                                            ; |DAC|clk_div:inst|clk_num~0                                                            ; out              ;
; |DAC|clk_div:inst|clk_num~1                                                            ; |DAC|clk_div:inst|clk_num~1                                                            ; out              ;
; |DAC|clk_div:inst|clk_num~2                                                            ; |DAC|clk_div:inst|clk_num~2                                                            ; out              ;
; |DAC|clk_div:inst|clk_num~3                                                            ; |DAC|clk_div:inst|clk_num~3                                                            ; out              ;
; |DAC|clk_div:inst|clk_num~4                                                            ; |DAC|clk_div:inst|clk_num~4                                                            ; out              ;
; |DAC|clk_div:inst|clk_num~5                                                            ; |DAC|clk_div:inst|clk_num~5                                                            ; out              ;
; |DAC|clk_div:inst|clk_num~6                                                            ; |DAC|clk_div:inst|clk_num~6                                                            ; out              ;
; |DAC|clk_div:inst|clk_num~7                                                            ; |DAC|clk_div:inst|clk_num~7                                                            ; out              ;
; |DAC|clk_div:inst|clk_num~8                                                            ; |DAC|clk_div:inst|clk_num~8                                                            ; out              ;
; |DAC|clk_div:inst|clk_num~9                                                            ; |DAC|clk_div:inst|clk_num~9                                                            ; out              ;
; |DAC|clk_div:inst|clk_num~10                                                           ; |DAC|clk_div:inst|clk_num~10                                                           ; out              ;
; |DAC|clk_div:inst|clk_num~11                                                           ; |DAC|clk_div:inst|clk_num~11                                                           ; out              ;
; |DAC|clk_div:inst|clk_num[1]                                                           ; |DAC|clk_div:inst|clk_num[1]                                                           ; regout           ;
; |DAC|clk_div:inst|clk_num[2]                                                           ; |DAC|clk_div:inst|clk_num[2]                                                           ; regout           ;
; |DAC|clk_div:inst|clk_num[3]                                                           ; |DAC|clk_div:inst|clk_num[3]                                                           ; regout           ;
; |DAC|clk_div:inst|clk_num[4]                                                           ; |DAC|clk_div:inst|clk_num[4]                                                           ; regout           ;
; |DAC|clk_div:inst|clk_num[5]                                                           ; |DAC|clk_div:inst|clk_num[5]                                                           ; regout           ;