📄 dac.sim.rpt
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; Group bus channels in simulation results ; Off ; Off ;
; Preserve fewer signal transitions to reduce memory requirements ; On ; On ;
; Trigger vector comparison with the specified mode ; INPUT_EDGE ; INPUT_EDGE ;
; Disable setup and hold time violations detection in input registers of bi-directional pins ; Off ; Off ;
; Overwrite Waveform Inputs With Simulation Outputs ; Off ; ;
; Perform Glitch Filtering in Timing Simulation ; Auto ; Auto ;
+--------------------------------------------------------------------------------------------+------------+---------------+
+----------------------+
; Simulation Waveforms ;
+----------------------+
Waveform report data cannot be output to ASCII.
Please use Quartus II to view the waveform report data.
+------------------------------------------------------------------------------------------+
; |DAC|ROM:inst2|altsyncram:altsyncram_component|altsyncram_b331:auto_generated|ALTSYNCRAM ;
+------------------------------------------------------------------------------------------+
Memory report data cannot be output to ASCII.
Please use Quartus II to view the memory report data.
+--------------------------------------------------------------------+
; Coverage Summary ;
+-----------------------------------------------------+--------------+
; Type ; Value ;
+-----------------------------------------------------+--------------+
; Total coverage as a percentage ; 51.33 % ;
; Total nodes checked ; 264 ;
; Total output ports checked ; 300 ;
; Total output ports with complete 1/0-value coverage ; 154 ;
; Total output ports with no 1/0-value coverage ; 146 ;
; Total output ports with no 1-value coverage ; 146 ;
; Total output ports with no 0-value coverage ; 146 ;
+-----------------------------------------------------+--------------+
The following table displays output ports that toggle between 1 and 0 during simulation.
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Complete 1/0-Value Coverage ;
+----------------------------------------------------------------------------------------------------------------+----------------------------------------------------------------------------------------------------------------+------------------+
; Node Name ; Output Port Name ; Output Port Type ;
+----------------------------------------------------------------------------------------------------------------+----------------------------------------------------------------------------------------------------------------+------------------+
; |DAC|da_clk ; |DAC|da_clk ; pin_out ;
; |DAC|clk_in ; |DAC|clk_in ; out ;
; |DAC|da_data[11] ; |DAC|da_data[11] ; pin_out ;
; |DAC|da_data[10] ; |DAC|da_data[10] ; pin_out ;
; |DAC|da_data[9] ; |DAC|da_data[9] ; pin_out ;
; |DAC|da_data[8] ; |DAC|da_data[8] ; pin_out ;
; |DAC|da_data[7] ; |DAC|da_data[7] ; pin_out ;
; |DAC|da_data[6] ; |DAC|da_data[6] ; pin_out ;
; |DAC|da_data[5] ; |DAC|da_data[5] ; pin_out ;
; |DAC|da_data[4] ; |DAC|da_data[4] ; pin_out ;
; |DAC|da_data[3] ; |DAC|da_data[3] ; pin_out ;
; |DAC|da_data[2] ; |DAC|da_data[2] ; pin_out ;
; |DAC|da_data[1] ; |DAC|da_data[1] ; pin_out ;
; |DAC|da_data[0] ; |DAC|da_data[0] ; pin_out ;
; |DAC|COUNTER:inst4|lpm_add_sub:lpm_add_sub_component|addcore:adder1_0[1]|unreg_res_node[11] ; |DAC|COUNTER:inst4|lpm_add_sub:lpm_add_sub_component|addcore:adder1_0[1]|unreg_res_node[11] ; out0 ;
; |DAC|COUNTER:inst4|lpm_add_sub:lpm_add_sub_component|addcore:adder1_0[1]|unreg_res_node[10] ; |DAC|COUNTER:inst4|lpm_add_sub:lpm_add_sub_component|addcore:adder1_0[1]|unreg_res_node[10] ; out0 ;
; |DAC|COUNTER:inst4|lpm_add_sub:lpm_add_sub_component|addcore:adder1_0[1]|unreg_res_node[9] ; |DAC|COUNTER:inst4|lpm_add_sub:lpm_add_sub_component|addcore:adder1_0[1]|unreg_res_node[9] ; out0 ;
; |DAC|COUNTER:inst4|lpm_add_sub:lpm_add_sub_component|addcore:adder1_0[1]|unreg_res_node[8] ; |DAC|COUNTER:inst4|lpm_add_sub:lpm_add_sub_component|addcore:adder1_0[1]|unreg_res_node[8] ; out0 ;
; |DAC|COUNTER:inst4|lpm_add_sub:lpm_add_sub_component|addcore:adder1_0[1]|unreg_res_node[7] ; |DAC|COUNTER:inst4|lpm_add_sub:lpm_add_sub_component|addcore:adder1_0[1]|unreg_res_node[7] ; out0 ;
; |DAC|COUNTER:inst4|lpm_add_sub:lpm_add_sub_component|addcore:adder1_0[1]|unreg_res_node[6] ; |DAC|COUNTER:inst4|lpm_add_sub:lpm_add_sub_component|addcore:adder1_0[1]|unreg_res_node[6] ; out0 ;
; |DAC|COUNTER:inst4|lpm_add_sub:lpm_add_sub_component|addcore:adder1_0[1]|unreg_res_node[5] ; |DAC|COUNTER:inst4|lpm_add_sub:lpm_add_sub_component|addcore:adder1_0[1]|unreg_res_node[5] ; out0 ;
; |DAC|COUNTER:inst4|lpm_add_sub:lpm_add_sub_component|addcore:adder1_0[1]|unreg_res_node[4] ; |DAC|COUNTER:inst4|lpm_add_sub:lpm_add_sub_component|addcore:adder1_0[1]|unreg_res_node[4] ; out0 ;
; |DAC|COUNTER:inst4|lpm_add_sub:lpm_add_sub_component|addcore:adder1_0[1]|unreg_res_node[3] ; |DAC|COUNTER:inst4|lpm_add_sub:lpm_add_sub_component|addcore:adder1_0[1]|unreg_res_node[3] ; out0 ;
; |DAC|COUNTER:inst4|lpm_add_sub:lpm_add_sub_component|addcore:adder1_0[1]|_~26 ; |DAC|COUNTER:inst4|lpm_add_sub:lpm_add_sub_component|addcore:adder1_0[1]|_~26 ; out0 ;
; |DAC|COUNTER:inst4|lpm_add_sub:lpm_add_sub_component|addcore:adder1_0[1]|_~27 ; |DAC|COUNTER:inst4|lpm_add_sub:lpm_add_sub_component|addcore:adder1_0[1]|_~27 ; out0 ;
; |DAC|COUNTER:inst4|lpm_add_sub:lpm_add_sub_component|addcore:adder1_0[1]|_~28 ; |DAC|COUNTER:inst4|lpm_add_sub:lpm_add_sub_component|addcore:adder1_0[1]|_~28 ; out0 ;
; |DAC|COUNTER:inst4|lpm_add_sub:lpm_add_sub_component|addcore:adder1_0[1]|_~29 ; |DAC|COUNTER:inst4|lpm_add_sub:lpm_add_sub_component|addcore:adder1_0[1]|_~29 ; out0 ;
; |DAC|COUNTER:inst4|lpm_add_sub:lpm_add_sub_component|addcore:adder1_0[1]|_~34 ; |DAC|COUNTER:inst4|lpm_add_sub:lpm_add_sub_component|addcore:adder1_0[1]|_~34 ; out0 ;
; |DAC|COUNTER:inst4|lpm_add_sub:lpm_add_sub_component|addcore:adder1_0[1]|_~41 ; |DAC|COUNTER:inst4|lpm_add_sub:lpm_add_sub_component|addcore:adder1_0[1]|_~41 ; out0 ;
; |DAC|COUNTER:inst4|lpm_add_sub:lpm_add_sub_component|addcore:adder1_0[1]|_~42 ; |DAC|COUNTER:inst4|lpm_add_sub:lpm_add_sub_component|addcore:adder1_0[1]|_~42 ; out0 ;
; |DAC|COUNTER:inst4|lpm_add_sub:lpm_add_sub_component|addcore:adder1_0[1]|_~43 ; |DAC|COUNTER:inst4|lpm_add_sub:lpm_add_sub_component|addcore:adder1_0[1]|_~43 ; out0 ;
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