dac.tan.rpt

DDS知识解析

+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Timing Analyzer Summary                                                                                                                                                                                                                                                                                                                                                                                                                   ;
+---------------------------------------------+-------+---------------+----------------------------------+---------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------------------------------------------------+------------------------------+------------------------------+--------------+
; Type                                        ; Slack ; Required Time ; Actual Time                      ; From                                                                                                          ; To                                                                                                                                  ; From Clock                   ; To Clock                     ; Failed Paths ;
+---------------------------------------------+-------+---------------+----------------------------------+---------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------------------------------------------------+------------------------------+------------------------------+--------------+
; Worst-case tsu                              ; N/A   ; None          ; 2.406 ns                         ; altera_internal_jtag~TMSUTAP                                                                                  ; sld_hub:sld_hub_inst|hub_mode_reg[1]                                                                                                ; --                           ; altera_internal_jtag~TCKUTAP ; 0            ;
; Worst-case tco                              ; N/A   ; None          ; 10.372 ns                        ; ROM:inst2|altsyncram:altsyncram_component|altsyncram_ta31:auto_generated|q_a[0]                               ; da_data[0]                                                                                                                          ; clk_in                       ; --                           ; 0            ;
; Worst-case tpd                              ; N/A   ; None          ; 3.106 ns                         ; altera_internal_jtag~TDO                                                                                      ; altera_reserved_tdo                                                                                                                 ; --                           ; --                           ; 0            ;
; Worst-case th                               ; N/A   ; None          ; 2.510 ns                         ; altera_internal_jtag~TDIUTAP                                                                                  ; sld_hub:sld_hub_inst|irsr_reg[8]                                                                                                    ; --                           ; altera_internal_jtag~TCKUTAP ; 0            ;
; Clock Setup: 'altera_internal_jtag~TCKUTAP' ; N/A   ; None          ; 101.65 MHz ( period = 9.838 ns ) ; sld_hub:sld_hub_inst|irf_reg[1][3]                                                                            ; sld_hub:sld_hub_inst|tdo                                                                                                            ; altera_internal_jtag~TCKUTAP ; altera_internal_jtag~TCKUTAP ; 0            ;
; Clock Setup: 'clk_in'                       ; N/A   ; None          ; 150.97 MHz ( period = 6.624 ns ) ; sld_signaltap:dds|sld_signaltap_impl:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|counter[6] ; sld_signaltap:dds|sld_signaltap_impl:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|last_buffer_write_address_sig[9] ; clk_in                       ; clk_in                       ; 0            ;
; Total number of failed paths                ;       ;               ;                                  ;                                                                                                               ;                                                                                                                                     ;                              ;                              ; 0            ;
+---------------------------------------------+-------+---------------+----------------------------------+---------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------------------------------------------------+------------------------------+------------------------------+--------------+


+--------------------------------------------------------------------------------------------------------------------+
; Timing Analyzer Settings                                                                                           ;
+---------------------------------------------------------------------+--------------------+------+----+-------------+
; Option                                                              ; Setting            ; From ; To ; Entity Name ;
+---------------------------------------------------------------------+--------------------+------+----+-------------+
; Device Name                                                         ; EP2C8Q208C8        ;      ;    ;             ;
; Timing Models                                                       ; Final              ;      ;    ;             ;
; Default hold multicycle                                             ; Same as Multicycle ;      ;    ;             ;
; Cut paths between unrelated clock domains                           ; On                 ;      ;    ;             ;
; Cut off read during write signal paths                              ; On                 ;      ;    ;             ;
; Cut off feedback from I/O pins                                      ; On                 ;      ;    ;             ;
; Report Combined Fast/Slow Timing                                    ; Off                ;      ;    ;             ;
; Ignore Clock Settings                                               ; Off                ;      ;    ;             ;
; Analyze latches as synchronous elements                             ; On                 ;      ;    ;             ;
; Enable Recovery/Removal analysis                                    ; Off                ;      ;    ;             ;
; Enable Clock Latency                                                ; Off                ;      ;    ;             ;
; Use TimeQuest Timing Analyzer                                       ; Off                ;      ;    ;             ;
; Minimum Core Junction Temperature                                   ; 0                  ;      ;    ;             ;
; Maximum Core Junction Temperature                                   ; 85                 ;      ;    ;             ;
; Number of source nodes to report per destination node               ; 10                 ;      ;    ;             ;