sin_add.vhd

来自「采用DDS技术的波形发生器(FPGA实现)」· VHDL 代码 · 共 26 行

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity sin_add is
port(clk:in std_logic;
     add_in:in std_logic_vector(9 downto 0);
     convert_value:out std_logic;--根据第10位判断是否要给rom值反转
     add_out:out std_logic_vector(7 downto 0));
end sin_add;

architecture add of sin_add is
begin
   process(clk)
     begin
     if rising_edge(clk) then
        if add_in(8)='1' then 
           add_out(7 downto 0)<=not add_in(7 downto 0);
        else add_out(7 downto 0)<=add_in(7 downto 0);
        end if;
       convert_value<=add_in(9);
      end if;
    end process;
end add;