dds.hier_info

采用DDS技术的波形发生器(FPGA实现)

data_out[1] <= LessThan0.DB_MAX_OUTPUT_PORT_TYPE
data_out[2] <= LessThan0.DB_MAX_OUTPUT_PORT_TYPE
data_out[3] <= LessThan0.DB_MAX_OUTPUT_PORT_TYPE
data_out[4] <= LessThan0.DB_MAX_OUTPUT_PORT_TYPE
data_out[5] <= LessThan0.DB_MAX_OUTPUT_PORT_TYPE
data_out[6] <= LessThan0.DB_MAX_OUTPUT_PORT_TYPE
data_out[7] <= LessThan0.DB_MAX_OUTPUT_PORT_TYPE


|dds|delta:inst9
address[0] => altsyncram:altsyncram_component.address_a[0]
address[1] => altsyncram:altsyncram_component.address_a[1]
address[2] => altsyncram:altsyncram_component.address_a[2]
address[3] => altsyncram:altsyncram_component.address_a[3]
address[4] => altsyncram:altsyncram_component.address_a[4]
address[5] => altsyncram:altsyncram_component.address_a[5]
address[6] => altsyncram:altsyncram_component.address_a[6]
address[7] => altsyncram:altsyncram_component.address_a[7]
clock => altsyncram:altsyncram_component.clock0
q[0] <= altsyncram:altsyncram_component.q_a[0]
q[1] <= altsyncram:altsyncram_component.q_a[1]
q[2] <= altsyncram:altsyncram_component.q_a[2]
q[3] <= altsyncram:altsyncram_component.q_a[3]
q[4] <= altsyncram:altsyncram_component.q_a[4]
q[5] <= altsyncram:altsyncram_component.q_a[5]
q[6] <= altsyncram:altsyncram_component.q_a[6]
q[7] <= altsyncram:altsyncram_component.q_a[7]


|dds|delta:inst9|altsyncram:altsyncram_component
wren_a => ~NO_FANOUT~
wren_b => ~NO_FANOUT~
rden_b => ~NO_FANOUT~
data_a[0] => ~NO_FANOUT~
data_a[1] => ~NO_FANOUT~
data_a[2] => ~NO_FANOUT~
data_a[3] => ~NO_FANOUT~
data_a[4] => ~NO_FANOUT~
data_a[5] => ~NO_FANOUT~
data_a[6] => ~NO_FANOUT~
data_a[7] => ~NO_FANOUT~
data_b[0] => ~NO_FANOUT~
address_a[0] => altsyncram_hq31:auto_generated.address_a[0]
address_a[1] => altsyncram_hq31:auto_generated.address_a[1]
address_a[2] => altsyncram_hq31:auto_generated.address_a[2]
address_a[3] => altsyncram_hq31:auto_generated.address_a[3]
address_a[4] => altsyncram_hq31:auto_generated.address_a[4]
address_a[5] => altsyncram_hq31:auto_generated.address_a[5]
address_a[6] => altsyncram_hq31:auto_generated.address_a[6]
address_a[7] => altsyncram_hq31:auto_generated.address_a[7]
address_b[0] => ~NO_FANOUT~
addressstall_a => ~NO_FANOUT~
addressstall_b => ~NO_FANOUT~
clock0 => altsyncram_hq31:auto_generated.clock0
clock1 => ~NO_FANOUT~
clocken0 => ~NO_FANOUT~
clocken1 => ~NO_FANOUT~
aclr0 => ~NO_FANOUT~
aclr1 => ~NO_FANOUT~
byteena_a[0] => ~NO_FANOUT~
byteena_b[0] => ~NO_FANOUT~
q_a[0] <= altsyncram_hq31:auto_generated.q_a[0]
q_a[1] <= altsyncram_hq31:auto_generated.q_a[1]
q_a[2] <= altsyncram_hq31:auto_generated.q_a[2]
q_a[3] <= altsyncram_hq31:auto_generated.q_a[3]
q_a[4] <= altsyncram_hq31:auto_generated.q_a[4]
q_a[5] <= altsyncram_hq31:auto_generated.q_a[5]
q_a[6] <= altsyncram_hq31:auto_generated.q_a[6]
q_a[7] <= altsyncram_hq31:auto_generated.q_a[7]
q_b[0] <= <GND>


|dds|delta:inst9|altsyncram:altsyncram_component|altsyncram_hq31:auto_generated
address_a[0] => ram_block1a0.PORTAADDR
address_a[0] => ram_block1a1.PORTAADDR
address_a[0] => ram_block1a2.PORTAADDR
address_a[0] => ram_block1a3.PORTAADDR
address_a[0] => ram_block1a4.PORTAADDR
address_a[0] => ram_block1a5.PORTAADDR
address_a[0] => ram_block1a6.PORTAADDR
address_a[0] => ram_block1a7.PORTAADDR
address_a[1] => ram_block1a0.PORTAADDR1
address_a[1] => ram_block1a1.PORTAADDR1
address_a[1] => ram_block1a2.PORTAADDR1
address_a[1] => ram_block1a3.PORTAADDR1
address_a[1] => ram_block1a4.PORTAADDR1
address_a[1] => ram_block1a5.PORTAADDR1
address_a[1] => ram_block1a6.PORTAADDR1
address_a[1] => ram_block1a7.PORTAADDR1
address_a[2] => ram_block1a0.PORTAADDR2
address_a[2] => ram_block1a1.PORTAADDR2
address_a[2] => ram_block1a2.PORTAADDR2
address_a[2] => ram_block1a3.PORTAADDR2
address_a[2] => ram_block1a4.PORTAADDR2
address_a[2] => ram_block1a5.PORTAADDR2
address_a[2] => ram_block1a6.PORTAADDR2
address_a[2] => ram_block1a7.PORTAADDR2
address_a[3] => ram_block1a0.PORTAADDR3
address_a[3] => ram_block1a1.PORTAADDR3
address_a[3] => ram_block1a2.PORTAADDR3
address_a[3] => ram_block1a3.PORTAADDR3
address_a[3] => ram_block1a4.PORTAADDR3
address_a[3] => ram_block1a5.PORTAADDR3
address_a[3] => ram_block1a6.PORTAADDR3
address_a[3] => ram_block1a7.PORTAADDR3
address_a[4] => ram_block1a0.PORTAADDR4
address_a[4] => ram_block1a1.PORTAADDR4
address_a[4] => ram_block1a2.PORTAADDR4
address_a[4] => ram_block1a3.PORTAADDR4
address_a[4] => ram_block1a4.PORTAADDR4
address_a[4] => ram_block1a5.PORTAADDR4
address_a[4] => ram_block1a6.PORTAADDR4
address_a[4] => ram_block1a7.PORTAADDR4
address_a[5] => ram_block1a0.PORTAADDR5
address_a[5] => ram_block1a1.PORTAADDR5
address_a[5] => ram_block1a2.PORTAADDR5
address_a[5] => ram_block1a3.PORTAADDR5
address_a[5] => ram_block1a4.PORTAADDR5
address_a[5] => ram_block1a5.PORTAADDR5
address_a[5] => ram_block1a6.PORTAADDR5
address_a[5] => ram_block1a7.PORTAADDR5
address_a[6] => ram_block1a0.PORTAADDR6
address_a[6] => ram_block1a1.PORTAADDR6
address_a[6] => ram_block1a2.PORTAADDR6
address_a[6] => ram_block1a3.PORTAADDR6
address_a[6] => ram_block1a4.PORTAADDR6
address_a[6] => ram_block1a5.PORTAADDR6
address_a[6] => ram_block1a6.PORTAADDR6
address_a[6] => ram_block1a7.PORTAADDR6
address_a[7] => ram_block1a0.PORTAADDR7
address_a[7] => ram_block1a1.PORTAADDR7
address_a[7] => ram_block1a2.PORTAADDR7
address_a[7] => ram_block1a3.PORTAADDR7
address_a[7] => ram_block1a4.PORTAADDR7
address_a[7] => ram_block1a5.PORTAADDR7
address_a[7] => ram_block1a6.PORTAADDR7
address_a[7] => ram_block1a7.PORTAADDR7
clock0 => ram_block1a0.CLK0
clock0 => ram_block1a1.CLK0
clock0 => ram_block1a2.CLK0
clock0 => ram_block1a3.CLK0
clock0 => ram_block1a4.CLK0
clock0 => ram_block1a5.CLK0
clock0 => ram_block1a6.CLK0
clock0 => ram_block1a7.CLK0
q_a[0] <= ram_block1a0.PORTADATAOUT
q_a[1] <= ram_block1a1.PORTADATAOUT
q_a[2] <= ram_block1a2.PORTADATAOUT
q_a[3] <= ram_block1a3.PORTADATAOUT
q_a[4] <= ram_block1a4.PORTADATAOUT
q_a[5] <= ram_block1a5.PORTADATAOUT
q_a[6] <= ram_block1a6.PORTADATAOUT
q_a[7] <= ram_block1a7.PORTADATAOUT


|dds|juchi_address:inst8
clk => addout[0]~reg0.CLK
clk => addout[1]~reg0.CLK
clk => addout[2]~reg0.CLK
clk => addout[3]~reg0.CLK
clk => addout[4]~reg0.CLK
clk => addout[5]~reg0.CLK
clk => addout[6]~reg0.CLK
clk => addout[7]~reg0.CLK
addin[0] => addout[0]~reg0.DATAIN
addin[1] => addout[1]~reg0.DATAIN
addin[2] => addout[2]~reg0.DATAIN
addin[3] => addout[3]~reg0.DATAIN
addin[4] => addout[4]~reg0.DATAIN
addin[5] => addout[5]~reg0.DATAIN
addin[6] => addout[6]~reg0.DATAIN
addin[7] => addout[7]~reg0.DATAIN
addin[8] => ~NO_FANOUT~
addin[9] => ~NO_FANOUT~
addout[0] <= addout[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
addout[1] <= addout[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
addout[2] <= addout[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
addout[3] <= addout[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
addout[4] <= addout[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE
addout[5] <= addout[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE
addout[6] <= addout[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE
addout[7] <= addout[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE


|dds|sin_out:inst4
clk => data_out[0]~reg0.CLK
clk => data_out[1]~reg0.CLK
clk => data_out[2]~reg0.CLK
clk => data_out[3]~reg0.CLK
clk => data_out[4]~reg0.CLK
clk => data_out[5]~reg0.CLK
clk => data_out[6]~reg0.CLK
clk => data_out[7]~reg0.CLK
data_convert => data_out~0.OUTPUTSELECT
data_convert => data_out~1.OUTPUTSELECT
data_convert => data_out~2.OUTPUTSELECT
data_convert => data_out~3.OUTPUTSELECT
data_convert => data_out~4.OUTPUTSELECT
data_convert => data_out~5.OUTPUTSELECT
data_convert => data_out~6.OUTPUTSELECT
data_convert => data_out~7.OUTPUTSELECT
rom[0] => data_out~7.DATAA
rom[0] => data_out~7.DATAB
rom[1] => data_out~6.DATAA
rom[1] => data_out~6.DATAB
rom[2] => data_out~5.DATAA
rom[2] => data_out~5.DATAB
rom[3] => data_out~4.DATAA
rom[3] => data_out~4.DATAB
rom[4] => data_out~3.DATAA
rom[4] => data_out~3.DATAB
rom[5] => data_out~2.DATAA
rom[5] => data_out~2.DATAB
rom[6] => data_out~1.DATAA
rom[6] => data_out~1.DATAB
rom[7] => data_out~0.DATAA
rom[7] => data_out~0.DATAB
data_out[0] <= data_out[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
data_out[1] <= data_out[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
data_out[2] <= data_out[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
data_out[3] <= data_out[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
data_out[4] <= data_out[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE
data_out[5] <= data_out[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE
data_out[6] <= data_out[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE
data_out[7] <= data_out[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE


|dds|sin_add:inst2
clk => convert_value~reg0.CLK
clk => add_out[0]~reg0.CLK
clk => add_out[1]~reg0.CLK
clk => add_out[2]~reg0.CLK
clk => add_out[3]~reg0.CLK
clk => add_out[4]~reg0.CLK
clk => add_out[5]~reg0.CLK
clk => add_out[6]~reg0.CLK
clk => add_out[7]~reg0.CLK
add_in[0] => add_out~7.DATAA
add_in[0] => add_out~7.DATAB
add_in[1] => add_out~6.DATAA
add_in[1] => add_out~6.DATAB
add_in[2] => add_out~5.DATAA
add_in[2] => add_out~5.DATAB
add_in[3] => add_out~4.DATAA
add_in[3] => add_out~4.DATAB
add_in[4] => add_out~3.DATAA
add_in[4] => add_out~3.DATAB
add_in[5] => add_out~2.DATAA
add_in[5] => add_out~2.DATAB
add_in[6] => add_out~1.DATAA
add_in[6] => add_out~1.DATAB
add_in[7] => add_out~0.DATAA
add_in[7] => add_out~0.DATAB
add_in[8] => add_out~0.OUTPUTSELECT
add_in[8] => add_out~1.OUTPUTSELECT
add_in[8] => add_out~2.OUTPUTSELECT
add_in[8] => add_out~3.OUTPUTSELECT
add_in[8] => add_out~4.OUTPUTSELECT
add_in[8] => add_out~5.OUTPUTSELECT
add_in[8] => add_out~6.OUTPUTSELECT
add_in[8] => add_out~7.OUTPUTSELECT
add_in[9] => convert_value~reg0.DATAIN
convert_value <= convert_value~reg0.DB_MAX_OUTPUT_PORT_TYPE
add_out[0] <= add_out[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
add_out[1] <= add_out[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
add_out[2] <= add_out[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
add_out[3] <= add_out[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
add_out[4] <= add_out[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE
add_out[5] <= add_out[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE
add_out[6] <= add_out[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE
add_out[7] <= add_out[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE


|dds|sinrom:inst3
address[0] => altsyncram:altsyncram_component.address_a[0]
address[1] => altsyncram:altsyncram_component.address_a[1]
address[2] => altsyncram:altsyncram_component.address_a[2]
address[3] => altsyncram:altsyncram_component.address_a[3]
address[4] => altsyncram:altsyncram_component.address_a[4]
address[5] => altsyncram:altsyncram_component.address_a[5]
address[6] => altsyncram:altsyncram_component.address_a[6]
address[7] => altsyncram:altsyncram_component.address_a[7]
clock => altsyncram:altsyncram_component.clock0
q[0] <= altsyncram:altsyncram_component.q_a[0]
q[1] <= altsyncram:altsyncram_component.q_a[1]
q[2] <= altsyncram:altsyncram_component.q_a[2]
q[3] <= altsyncram:altsyncram_component.q_a[3]
q[4] <= altsyncram:altsyncram_component.q_a[4]
q[5] <= altsyncram:altsyncram_component.q_a[5]
q[6] <= altsyncram:altsyncram_component.q_a[6]
q[7] <= altsyncram:altsyncram_component.q_a[7]


|dds|sinrom:inst3|altsyncram:altsyncram_component
wren_a => ~NO_FANOUT~
wren_b => ~NO_FANOUT~
rden_b => ~NO_FANOUT~
data_a[0] => ~NO_FANOUT~
data_a[1] => ~NO_FANOUT~
data_a[2] => ~NO_FANOUT~
data_a[3] => ~NO_FANOUT~
data_a[4] => ~NO_FANOUT~
data_a[5] => ~NO_FANOUT~
data_a[6] => ~NO_FANOUT~
data_a[7] => ~NO_FANOUT~
data_b[0] => ~NO_FANOUT~
address_a[0] => altsyncram_hk31:auto_generated.address_a[0]
address_a[1] => altsyncram_hk31:auto_generated.address_a[1]
address_a[2] => altsyncram_hk31:auto_generated.address_a[2]
address_a[3] => altsyncram_hk31:auto_generated.address_a[3]
address_a[4] => altsyncram_hk31:auto_generated.address_a[4]
address_a[5] => altsyncram_hk31:auto_generated.address_a[5]
address_a[6] => altsyncram_hk31:auto_generated.address_a[6]
address_a[7] => altsyncram_hk31:auto_generated.address_a[7]
address_b[0] => ~NO_FANOUT~
addressstall_a => ~NO_FANOUT~
addressstall_b => ~NO_FANOUT~
clock0 => altsyncram_hk31:auto_generated.clock0
clock1 => ~NO_FANOUT~
clocken0 => ~NO_FANOUT~
clocken1 => ~NO_FANOUT~
aclr0 => ~NO_FANOUT~
aclr1 => ~NO_FANOUT~
byteena_a[0] => ~NO_FANOUT~
byteena_b[0] => ~NO_FANOUT~
q_a[0] <= altsyncram_hk31:auto_generated.q_a[0]
q_a[1] <= altsyncram_hk31:auto_generated.q_a[1]
q_a[2] <= altsyncram_hk31:auto_generated.q_a[2]
q_a[3] <= altsyncram_hk31:auto_generated.q_a[3]
q_a[4] <= altsyncram_hk31:auto_generated.q_a[4]
q_a[5] <= altsyncram_hk31:auto_generated.q_a[5]
q_a[6] <= altsyncram_hk31:auto_generated.q_a[6]
q_a[7] <= altsyncram_hk31:auto_generated.q_a[7]
q_b[0] <= <GND>


|dds|sinrom:inst3|altsyncram:altsyncram_component|altsyncram_hk31:auto_generated
address_a[0] => ram_block1a0.PORTAADDR
address_a[0] => ram_block1a1.PORTAADDR
address_a[0] => ram_block1a2.PORTAADDR
address_a[0] => ram_block1a3.PORTAADDR
address_a[0] => ram_block1a4.PORTAADDR
address_a[0] => ram_block1a5.PORTAADDR
address_a[0] => ram_block1a6.PORTAADDR
address_a[0] => ram_block1a7.PORTAADDR
address_a[1] => ram_block1a0.PORTAADDR1
address_a[1] => ram_block1a1.PORTAADDR1
address_a[1] => ram_block1a2.PORTAADDR1
address_a[1] => ram_block1a3.PORTAADDR1
address_a[1] => ram_block1a4.PORTAADDR1
address_a[1] => ram_block1a5.PORTAADDR1
address_a[1] => ram_block1a6.PORTAADDR1
address_a[1] => ram_block1a7.PORTAADDR1
address_a[2] => ram_block1a0.PORTAADDR2
address_a[2] => ram_block1a1.PORTAADDR2
address_a[2] => ram_block1a2.PORTAADDR2
address_a[2] => ram_block1a3.PORTAADDR2
address_a[2] => ram_block1a4.PORTAADDR2
address_a[2] => ram_block1a5.PORTAADDR2
address_a[2] => ram_block1a6.PORTAADDR2
address_a[2] => ram_block1a7.PORTAADDR2
address_a[3] => ram_block1a0.PORTAADDR3
address_a[3] => ram_block1a1.PORTAADDR3
address_a[3] => ram_block1a2.PORTAADDR3
address_a[3] => ram_block1a3.PORTAADDR3
address_a[3] => ram_block1a4.PORTAADDR3
address_a[3] => ram_block1a5.PORTAADDR3
address_a[3] => ram_block1a6.PORTAADDR3
address_a[3] => ram_block1a7.PORTAADDR3
address_a[4] => ram_block1a0.PORTAADDR4
address_a[4] => ram_block1a1.PORTAADDR4
address_a[4] => ram_block1a2.PORTAADDR4
address_a[4] => ram_block1a3.PORTAADDR4
address_a[4] => ram_block1a4.PORTAADDR4
address_a[4] => ram_block1a5.PORTAADDR4
address_a[4] => ram_block1a6.PORTAADDR4
address_a[4] => ram_block1a7.PORTAADDR4
address_a[5] => ram_block1a0.PORTAADDR5
address_a[5] => ram_block1a1.PORTAADDR5
address_a[5] => ram_block1a2.PORTAADDR5
address_a[5] => ram_block1a3.PORTAADDR5
address_a[5] => ram_block1a4.PORTAADDR5
address_a[5] => ram_block1a5.PORTAADDR5
address_a[5] => ram_block1a6.PORTAADDR5
address_a[5] => ram_block1a7.PORTAADDR5
address_a[6] => ram_block1a0.PORTAADDR6
address_a[6] => ram_block1a1.PORTAADDR6
address_a[6] => ram_block1a2.PORTAADDR6
address_a[6] => ram_block1a3.PORTAADDR6
address_a[6] => ram_block1a4.PORTAADDR6
address_a[6] => ram_block1a5.PORTAADDR6
address_a[6] => ram_block1a6.PORTAADDR6
address_a[6] => ram_block1a7.PORTAADDR6
address_a[7] => ram_block1a0.PORTAADDR7
address_a[7] => ram_block1a1.PORTAADDR7
address_a[7] => ram_block1a2.PORTAADDR7
address_a[7] => ram_block1a3.PORTAADDR7
address_a[7] => ram_block1a4.PORTAADDR7
address_a[7] => ram_block1a5.PORTAADDR7
address_a[7] => ram_block1a6.PORTAADDR7
address_a[7] => ram_block1a7.PORTAADDR7
clock0 => ram_block1a0.CLK0
clock0 => ram_block1a1.CLK0
clock0 => ram_block1a2.CLK0
clock0 => ram_block1a3.CLK0
clock0 => ram_block1a4.CLK0
clock0 => ram_block1a5.CLK0
clock0 => ram_block1a6.CLK0
clock0 => ram_block1a7.CLK0
q_a[0] <= ram_block1a0.PORTADATAOUT
q_a[1] <= ram_block1a1.PORTADATAOUT
q_a[2] <= ram_block1a2.PORTADATAOUT
q_a[3] <= ram_block1a3.PORTADATAOUT
q_a[4] <= ram_block1a4.PORTADATAOUT
q_a[5] <= ram_block1a5.PORTADATAOUT
q_a[6] <= ram_block1a6.PORTADATAOUT
q_a[7] <= ram_block1a7.PORTADATAOUT